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/Documentation/devicetree/bindings/net/
Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
29 Specifies the index of the FMan unit.
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
[all …]
Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
Dfsl,fman-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
21 - fsl,fman-v2-port-oh
22 - fsl,fman-v2-port-rx
23 - fsl,fman-v2-port-tx
24 - fsl,fman-v3-port-oh
25 - fsl,fman-v3-port-rx
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Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
/Documentation/devicetree/bindings/powerpc/fsl/
Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
[all …]
Dsrio.txt5 - compatible
11 Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
15 - reg
17 Value type: <prop-encoded-array>
22 - interrupts
24 Value type: <prop_encoded-array>
31 property. (Typically shared with port-write).
33 - fsl,srio-rmu-handle:
37 (See srio-rmu.txt for more details on RMU node binding)
43 - cell-index
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/Documentation/devicetree/bindings/ata/
Dfsl-sata.txt3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
10 "fsl,pq-sata"
11 - interrupts : <interrupt mapping for SATA IRQ>
12 - cell-index : controller index.
19 - reg : <registers mapping>
23 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
25 cell-index = <1>;
27 interrupt-parent = < &ipic >;
/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
[all …]
Dcib.txt4 - compatible: "cavium,octeon-7130-cib"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: Two elements consisting of the addresses of the RAW and EN
13 - cavium,max-bits: The index (zero based) of the highest numbered bit
16 - interrupts: The CIU line to which the CIB block is connected.
18 - #interrupt-cells: Must be <2>. The first cell is the bit within the
19 CIB. The second cell specifies the triggering semantics of the
24 interrupt-controller@107000000e000 {
25 compatible = "cavium,octeon-7130-cib";
28 cavium,max-bits = <23>;
[all …]
/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt3 Device nodes needed for operation of the ppc440spe-adma driver
6 by ADMA driver for configuration of RAID-6 H/W capabilities of
15 - compatible : "ibm,i2o-440spe";
16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
22 compatible = "ibm,i2o-440spe";
24 dcr-reg = <0x060 0x020>;
32 - compatible : "ibm,dma-440spe";
33 - cell-index : 1 cell, hardware index of the DMA engine
35 - reg : <registers mapping>
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/Documentation/devicetree/bindings/spi/
Dfsl-spi.txt4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
19 The gpios will be referred to as reg = <index> in the SPI child nodes.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
24 the cs-gpios property is not present.
[all …]
Dspi-orion.txt4 - compatible : should be on of the following:
5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
11 - reg : offset and length of the register set for the device.
19 chip-select lines 0 through 7 respectively.
20 - cell-index : Which of multiple SPI controllers is this.
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
28 - #interrupt-cells: Specifies the number of cells needed to encode an
[all …]
Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
[all …]
Dinterrupts.txt5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
44 a) one cell
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,gsbi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 representing a serial sub-node device that is mux'd as part of the GSBI
26 const: qcom,gsbi-v1.0.0
28 '#address-cells':
31 cell-index:
[all …]
/Documentation/devicetree/bindings/mailbox/
Dnvidia,tegra186-hsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 contain two cells. The first cell determines the HSP type and the
26 second cell is used to identify the mailbox that the client is going
29 For shared mailboxes, the first cell composed of two fields:
30 - bits 15..8:
[all …]
/Documentation/devicetree/bindings/clock/
Dalphascale,acc.txt7 - compatible: must be "alphascale,asm9260-clock-controller"
8 - reg: must contain the ACC register base and size
9 - #clock-cells : shall be set to 1.
11 Simple one-cell clock specifier format is used, where the only cell is used
12 as an index of the clock inside the provider.
13 It is encouraged to use dt-binding for clock index definitions. SoC specific
14 dt-binding should be included to the device tree descriptor. For example
16 #include <dt-bindings/clock/alphascale,asm9260.h>
19 _AHB_ - AHB gate;
20 _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
[all …]
/Documentation/devicetree/bindings/dma/
Drenesas,rzn1-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
23 '#dma-cells':
27 cell gives the DMA mux bit index that must be set starting from 0. The
28 sixth cell gives the binary value that must be written there, ie. 0 or 1.
[all …]
/Documentation/devicetree/bindings/reset/
Dti-syscon-reset.txt6 typically provided by means of memory-mapped I/O registers. These registers are
22 --------------------
23 - compatible : Should be,
24 "ti,k2e-pscrst"
25 "ti,k2l-pscrst"
26 "ti,k2hk-pscrst"
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
33 Cell #1 : offset of the reset assert control
[all …]
/Documentation/devicetree/bindings/soc/ti/
Dsci-pm-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI generic power domain
10 - Nishanth Menon <nm@ti.com>
13 - $ref: /schemas/power/power-domain.yaml#
20 through a protocol called TI System Control Interface (TI-SCI protocol).
22 This PM domain node represents the global PM domain managed by the TI-SCI
24 the TI-SCI controller, it must be a child of the TI-SCI controller node.
[all …]
/Documentation/devicetree/bindings/pwm/
Dcirrus,clps711x-pwm.txt4 - compatible: Shall contain "cirrus,ep7209-pwm".
5 - reg: Physical base address and length of the controller's registers.
6 - clocks: phandle + clock specifier pair of the PWM reference clock.
7 - #pwm-cells: Should be 1. The cell specifies the index of the channel.
11 compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
14 #pwm-cells = <1>;

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