Home
last modified time | relevance | path

Searched full:cell (Results 1 – 25 of 542) sorted by relevance

12345678910>>...22

/Documentation/devicetree/bindings/net/
Dibm,emac.txt24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
26 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
28 - cell-index : 1 cell, hardware index of the EMAC cell on a given
31 - max-frame-size : 1 cell, maximum frame size supported in bytes
32 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
35 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
38 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
41 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
48 - mdio-device : 1 cell, required iff using shared MDIO registers
51 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
[all …]
Dfsl,fman.yaml26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
36 register[bit] FMan unit cell-index
41 register[bit] FMan unit cell-index
48 register[bit] FMan unit cell-index
91 channels in the FMan. The first cell specifies the beginning
92 of the range and the second cell specifies the number of
95 - description: The first cell specifies the beginning of the range.
97 The second cell specifies the number of channels.
[all …]
Dbroadcom-bcm87xx.txt9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
11 address within the MMD, the third cell contains a mask to be ANDed
12 with the existing register value, and the fourth cell is ORed with
13 he result to yield the new register value. If the third cell has a
/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
[all …]
/Documentation/devicetree/bindings/nvmem/layouts/
Dfixed-cell.yaml4 $id: http://devicetree.org/schemas/nvmem/layouts/fixed-cell.yaml#
7 title: Fixed offset & size NVMEM cell
18 Cell with base MAC address to be used for calculating extra relative
20 It can be stored in a plain binary format (cell length 6) or as an
21 ASCII text like "00:11:22:33:44:55" (cell length 17).
46 "#nvmem-cell-cells":
50 - "#nvmem-cell-cells"
/Documentation/devicetree/bindings/powerpc/4xx/
Dcpm.txt16 - unused-units : specifier consist of one cell. For each
17 bit in the cell, the corresponding bit
20 - idle-doze : specifier consist of one cell. For each
21 bit in the cell, the corresponding bit
24 - standby : specifier consist of one cell. For each
25 bit in the cell, the corresponding bit
28 - suspend : specifier consist of one cell. For each
29 bit in the cell, the corresponding bit
/Documentation/devicetree/bindings/interrupt-controller/
Dcdns,xtensa-pic.txt8 When it's 1, the first cell is the internal IRQ number.
9 When it's 2, the first cell is the IRQ number, and the second cell
19 /* one cell: internal irq number,
20 * two cells: second cell == 0: internal irq number
21 * second cell == 1: external irq number
Dcdns,xtensa-mx.txt12 /* one cell: internal irq number,
13 * two cells: second cell == 0: internal irq number
14 * second cell == 1: external irq number
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic.txt85 <1st-cell> interrupt-number
90 Note: If the interrupt-type cell is undefined
91 (i.e. #interrupt-cells = 2), this cell
96 <2nd-cell> level-sense information, encoded as follows:
102 <3rd-cell> interrupt-type
108 The interrupt-number cell contains
110 type-specific cell is undefined. The
121 The interrupt-number cell contains
124 cell identifies the specific error
129 The interrupt-number cell identifies
[all …]
Ddma.txt14 - cell-index : controller index. 0 for controller @ 0x8100
21 - cell-index : DMA channel index starts at 0.
37 cell-index = <0>;
40 cell-index = <0>;
47 cell-index = <1>;
54 cell-index = <2>;
61 cell-index = <3>;
78 - cell-index : controller index. 0 for controller @ 0x21000,
86 - cell-index : DMA channel index starts at 0.
97 cell-index = <0>;
[all …]
/Documentation/ABI/testing/
Dsysfs-nvmem-cells1 What: /sys/bus/nvmem/devices/.../cells/<cell-name>
6 The "cells" folder contains one file per cell exposed by the
8 with <name> being the cell name and <where> its location in
11 the file is the size of the cell (when known). The content of
12 the file is the binary content of the cell (may sometimes be
/Documentation/devicetree/bindings/thermal/
Dsprd-thermal.yaml35 nvmem-cell-names:
65 nvmem-cell-names:
71 - nvmem-cell-names
81 - nvmem-cell-names
96 nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal";
103 nvmem-cell-names = "sen_delta_cal";
109 nvmem-cell-names = "sen_delta_cal";
/Documentation/devicetree/bindings/clock/
Dstericsson,u8500-clks.yaml38 description: A subnode with one clock cell for PRCMU (power, reset, control
39 management unit) clocks. The cell indicates which PRCMU clock in the
51 reset and clock controller) peripheral clocks. The first cell indicates
53 5, 6. The second cell indicates which clock inside the PRCC block it
65 and clock controller) kernel clocks. The first cell indicates which PRCC
67 second cell indicates which clock inside the PRCC block it wants, possible
79 PRCC (peripheral reset and clock controller). The first cell indicates
81 5 and 6. The second cell indicates which reset line inside the PRCC block
121 The first cell indicates which output clock we are using,
123 The second cell indicates which clock we want to use as source,
[all …]
/Documentation/userspace-api/media/v4l/
Dext-ctrls-detect.rst37 - The image is divided into a grid, each cell with its own motion
41 - The image is divided into a grid, each cell with its own region
55 Sets the motion detection thresholds for each cell in the grid. To
57 detection mode. Matrix element (0, 0) represents the cell at the
61 Sets the motion detection region value for each cell in the grid. To
63 detection mode. Matrix element (0, 0) represents the cell at the
/Documentation/driver-api/
Dnvmem.rst81 Additionally it is possible to create nvmem cell lookup entries and register
99 3. NVMEM cell based consumer APIs
108 void nvmem_cell_put(struct nvmem_cell *cell);
109 void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);
111 void *nvmem_cell_read(struct nvmem_cell *cell, ssize_t *len);
112 int nvmem_cell_write(struct nvmem_cell *cell, void *buf, ssize_t len);
114 `*nvmem_cell_get()` apis will get a reference to nvmem cell for a given id,
115 and nvmem_cell_read/write() can then read or write to the cell.
116 Once the usage of the cell is finished the consumer should call
117 `*nvmem_cell_put()` to free all the allocation memory for the cell.
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-thunderx.txt7 - First cell is the GPIO pin number relative to the controller.
8 - Second cell is a standard generic flag bitfield as described in gpio.txt.
15 - First cell is the GPIO pin number relative to the controller.
16 - Second cell is triggering flags as defined in interrupts.txt.
Dgpio-twl4030.txt7 - first cell is the pin number
8 - second cell is used to specify optional parameters (unused)
12 The first cell is the GPIO number.
13 The second cell is not used.
Dcdns,gpio.txt7 * first cell is the GPIO number.
8 * second cell specifies the GPIO flags, as defined in
22 * first cell is the GPIO number you want to use as an IRQ source.
23 * second cell specifies the IRQ type, as defined in
Dgpio-altera.txt8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
13 - The first cell is the GPIO offset number within the GPIO controller.
14 - The second cell is the interrupt trigger type and level flags.
/Documentation/filesystems/
Dafs.rst14 - The cell database.
64 When inserting the driver modules the root cell must be specified along with a
83 Where the parameters to the "add" command are the name of a cell and a list of
84 volume location servers within that cell, with the latter separated by colons.
89 mount -t afs "#cambridge.redhat.com:root.cell." /afs/cambridge
91 mount -t afs "#root.cell." /afs/cambridge
100 The name of the cell is optional, and if not given during a mount, then the
101 named volume will be looked up in the cell specified during modprobe.
139 looks up a cell of the same name, for example::
156 (*) A directory per cell that contains files that list volume location
[all …]
/Documentation/devicetree/bindings/reset/
Dti-syscon-reset.txt33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
37 Cell #3 : offset of the reset deassert control
39 Cell #4 : bit position of the reset in the reset
41 Cell #5 : offset of the reset status register
43 Cell #6 : bit position of the reset in the
45 Cell #7 : Flags used to control reset behavior,
/Documentation/devicetree/bindings/
Djailhouse.txt1 Jailhouse non-root cell device tree bindings
4 When running in a non-root Jailhouse cell (partition), the device tree of this
8 - compatible = "jailhouse,cell"
/Documentation/devicetree/bindings/iio/adc/
Dsprd,sc2720-adc.yaml39 nvmem-cell-names: true
53 nvmem-cell-names:
62 nvmem-cell-names:
78 - nvmem-cell-names
96 nvmem-cell-names = "big_scale_calib", "small_scale_calib";
115 nvmem-cell-names = "big_scale_calib1", "big_scale_calib2",
/Documentation/devicetree/bindings/power/reset/
Dnvmem-reboot-mode.yaml14 and stores it in the NVMEM cell named "reboot-mode". The bootloader can
27 nvmem-cell-names:
37 - nvmem-cell-names
46 nvmem-cell-names = "reboot-mode";
/Documentation/devicetree/bindings/firmware/
Dcznic,turris-omnia-mcu.yaml32 The first cell specifies the interrupt number (0 to 63), the second cell
52 The first cell is bank number (0, 1 or 2), the second cell is pin number
54 third cell specifies consumer flags.

12345678910>>...22