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/Documentation/devicetree/bindings/powerpc/fsl/
Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/Documentation/devicetree/bindings/dma/
Dmv-xor.txt4 - compatible: Should be one of the following:
5 - "marvell,orion-xor"
6 - "marvell,armada-380-xor"
7 - "marvell,armada-3700-xor".
8 - reg: Should contain registers location and length (two sets)
11 - clocks: pointer to the reference clock
13 The DT node must also contains sub-nodes for each XOR channel that the
14 XOR engine has. Those sub-nodes have the following required
16 - interrupts: interrupt of the XOR channel
18 The sub-nodes used to contain one or several of the following
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Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
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Dk3dma.txt6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
15 - clocks: clock required
21 compatible = "hisilicon,k3-dma-1.0";
[all …]
Dcirrus,ep9301-dma-m2m.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2m
20 - items:
21 - enum:
[all …]
Dti-edma.txt3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
5 responsible for the DMA channel handling, while the TCs are responsible to
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17 channel controller(s) on 66AK2G.
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
[all …]
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
42 20: SLIMbus or HSI channel 0
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
15 Please refer to interrupts.txt in this directory for details of the common
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
29 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
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Dfsl,irqsteer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
15 - const: fsl,imx-irqsteer
16 - items:
17 - enum:
18 - fsl,imx8m-irqsteer
19 - fsl,imx8mp-irqsteer
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/Documentation/virt/hyperv/
Dvmbus.rst1 .. SPDX-License-Identifier: GPL-2.0
5 VMBus is a software construct provided by Hyper-V to guest VMs. It
7 devices that Hyper-V presents to guest VMs. The control path is
11 and the synthetic device implementation that is part of Hyper-V, and
12 signaling primitives to allow Hyper-V and the guest to interrupt
17 establishes the VMBus control path with the Hyper-V host, then
21 Most synthetic devices offered by Hyper-V have a corresponding Linux
29 * PCI device pass-thru
34 * Key/Value Pair (KVP) exchange with Hyper-V
35 * Hyper-V online backup (a.k.a. VSS)
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/Documentation/devicetree/bindings/sound/
Dsprd-mcdt.txt1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
5 supports 10 DAC channel and 10 ADC channel, and each channel can be
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
18 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
Dimg,i2s-in.txt5 - compatible : Compatible list, must contain "img,i2s-in"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entry:
16 - dmas: Contains an entry for each entry in dma-names.
18 - dma-names: Must include the following entry:
19 "rx" Single DMA channel used by all active I2S channels
21 - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
25 - interrupts : Contains the I2S in interrupts. Depending on
[all …]
Dimg,i2s-out.txt5 - compatible : Compatible list, must contain "img,i2s-out"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entries:
17 - dmas: Contains an entry for each entry in dma-names.
19 - dma-names: Must include the following entry:
20 "tx" Single DMA channel used by all active I2S channels
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
[all …]
/Documentation/devicetree/bindings/mailbox/
Darm,mhuv3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Cristian Marussi <cristian.marussi@arm.com>
27 - Configure the MHU
28 - Send Transfers to the Receiver
29 - Optionally receive acknowledgment of a Transfer from the Receiver
32 - Configure the MHU
33 - Receive Transfers from the Sender
[all …]
Dfsl,mu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 for one processor to signal the other processor using interrupts.
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
[all …]
Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
24 compatible = "apm,xgene-slimpro-mbox";
[all …]
Darm,mhuv2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
16 communication with remote processor(s), where the number of channel windows
24 If the interrupts property is present in device tree node, then its treated as
33 - Data-transfer: Each transfer is made of one or more words, using one or more
34 channel windows.
[all …]
/Documentation/devicetree/bindings/dma/xilinx/
Dxilinx_dma.txt2 It can be configured to have one channel or two channels. If configured
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
[all …]
/Documentation/devicetree/bindings/iio/adc/
Drenesas,rzg2l-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
16 stored in a 32-bit data register corresponding to each channel.
21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
[all …]
Dallwinner,sun20i-d1-gpadc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/allwinner,sun20i-d1-gpadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maksim Kiselev <bigunclemax@gmail.com>
15 - enum:
16 - allwinner,sun20i-d1-gpadc
17 - items:
18 - enum:
19 - allwinner,sun50i-h616-gpadc
[all …]
Denvelope-detector.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/envelope-detector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
18 input +------>-------|+ \
20 .-------. | }---.
22 | dac|-->--|- / |
26 | irq|------<-------'
28 '-------'
[all …]
Dnxp,imx93-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haibo Chen <haibo.chen@nxp.com>
13 The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels
15 One-Shot and Scan (continuous) conversions. Programmable DMA
16 enables for each channel Also this ADC contain alternate analog
18 also has Self-test logic and Software-initiated calibration.
22 const: nxp,imx93-adc
[all …]
Dti,tsc2046.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - ti,tsc2046e-adc
23 interrupts:
26 vref-supply:
29 "#io-channel-cells":
32 '#address-cells':
35 '#size-cells':
[all …]
/Documentation/devicetree/bindings/iio/proximity/
Dtyhx,hx9023s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yasin Lee <yasin.lee.x@gmail.com>
23 interrupts:
29 vdd-supply: true
31 "#address-cells":
34 "#size-cells":
38 "^channel@[0-4]$":
47 description: The channel number.
[all …]
/Documentation/devicetree/bindings/thermal/
Dsamsung,exynos-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/samsung,exynos-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 For multi-instance tmu each instance should have an alias correctly numbered
19 - samsung,exynos3250-tmu
20 - samsung,exynos4412-tmu
21 - samsung,exynos4210-tmu
22 - samsung,exynos5250-tmu
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