Searched +full:chip +full:- +full:id (Results 1 – 25 of 539) sorted by relevance
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
21 48 hardware channels to access analog chip. For 2 software read/write channels,
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| D | cdns,qspi-nor-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
22 cdns,tshsl-ns:
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| /Documentation/devicetree/bindings/mtd/ |
| D | st,stm32-fmc2-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
28 - description: tx DMA channel
29 - description: rx DMA channel
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| D | nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
17 enforced even for simple controllers supporting only one chip.
21 pattern: "^nand-controller(@.*)?"
23 "#address-cells":
26 "#size-cells":
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| D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
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| D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
19 {size} bytes for a particular raw NAND chip.
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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| D | spi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/spi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
18 const: spi-nand
21 description: Encode the chip-select line on the SPI bus
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
13 amount of individual LPDDR chips and the ranks per chip.
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-platform-kunpeng_hccs | 9 contains read-only attributes exposing some summarization
10 information of all HCCS ports under a specified chip.
11 The X in 'chipX' indicates the Xth chip on platform.
16 all_linked: (RO) if all enabled ports on this chip are
18 linked_full_lane: (RO) if all linked ports on this chip are full
21 chip.
32 contains read-only attributes exposing some summarization
34 The Y in 'dieY' indicates the hardware id of the die on chip who
35 has chip id X.
60 contains read-only attributes exposing information about
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| D | sysfs-driver-w1_ds28e17 | 1 What: /sys/bus/w1/devices/19-<id>/speed
6 DS28E17 chip. When read, it reads the current setting from
7 the DS28E17 chip.
14 What: /sys/bus/w1/devices/19-<id>/stretch
20 chip. When read, returns the current setting.
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| D | sysfs-driver-jz4780-efuse | 1 What: /sys/devices/*/<our-device>/nvmem
4 Description: read-only access to the efuse on the Ingenic JZ4780 SoC
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
19 Users: any user space application which wants to read the Chip
20 and Customer ID
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| D | sysfs-firmware-opal-psr | 3 Contact: Linux for PowerPC mailing list <linuxppc-dev@lists.ozlabs.org>
4 Description: Power-Shift-Ratio directory for Powernv P9 servers
6 Power-Shift-Ratio allows to provide hints the firmware
13 Contact: Linux for PowerPC mailing list <linuxppc-dev@lists.ozlabs.org>
16 Power-Shift-Ratio between CPU and GPU for a given chip
17 with chip-id X. This file gives the ratio (0-100)
18 which is used by OCC for power-capping.
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/fsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eddie James <eajames@linux.ibm.com>
18 "#address-cells":
21 "#size-cells":
24 '#interrupt-cells':
27 bus-frequency:
31 interrupt-controller: true
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| /Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 7 - compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
12 o CPU chip regs:
15 functionalities: chip ID, general purpose register for software use, reset
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
35 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
36 - reg : Should contain registers location and length
40 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
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| /Documentation/admin-guide/gpio/ |
| D | gpio-mockup.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
8 This module has been obsoleted by the more flexible gpio-sim.rst.
14 The GPIO Testing Driver (gpio-mockup) provides a way to create simulated GPIO
20 --------------------------------------------
22 When loading the gpio-mockup driver a number of parameters can be passed to the
28 pairs. Each pair defines the base GPIO number (non-negative integer)
29 and the first number after the last of this chip. If the base GPIO
30 is -1, the gpiolib will assign it automatically. while the following
31 parameter is the number of lines exposed by the chip.
33 Example: gpio_mockup_ranges=-1,8,-1,16,405,409
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| /Documentation/devicetree/bindings/reset/ |
| D | marvell,berlin2-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Antoine Tenart <atenart@kernel.org>
13 description: The reset controller node must be a sub-node of the chip
18 const: marvell,berlin2-reset
20 "#reset-cells":
24 - compatible
25 - "#reset-cells"
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | sensor-groups.txt | 2 -------------------------------
4 Node: /ibm,opal/sensor-groups
9 - compatible : Should be "ibm,opal-sensor-group"
13 - type : String to indicate the type of sensor-group
15 - sensor-group-id: Abstract unique identifier provided by firmware of
16 type <u32> which is used for sensor-group
20 - ibm,chip-id : Chip ID
22 - sensors : Phandle array of child nodes of /ibm,opal/sensor/
25 - ops : Array of opal-call numbers indicating available operations on
|
| /Documentation/sound/kernel-api/ |
| D | writing-an-alsa-driver.rst | 11 Architecture) <http://www.alsa-project.org/>`__ driver. The document
19 low-level driver implementation details. It only describes the standard
26 -------
56 --------------
60 sub-directories contain different modules and are dependent upon the
74 This directory and its sub-directories are for the ALSA sequencer. This
76 as snd-seq-midi, snd-seq-virmidi, etc. They are compiled only when
85 -----------------
88 to be exported to user-space, or included by several files in different
94 -----------------
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| /Documentation/scsi/ |
| D | 53c700.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 This driver supports the 53c700 and 53c700-66 chips. It also supports
12 does sync (-66 and 710 only), disconnects and tag command queueing.
33 Using the Chip Core Driver
36 In order to plumb the 53c700 chip core driver into a working SCSI
37 driver, you need to know three things about the way the chip is wired
45 the SCSI Id from the card bios or whether the chip is wired for
54 asynchronous dividers for the chip. As a general rule of thumb,
56 consistent with the best operation of the chip (although some choose
58 of an extra clock chip). The best operation clock speeds are:
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| /Documentation/devicetree/bindings/devfreq/event/ |
| D | samsung,exynos-nocp.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos NoC (Network on Chip) Probe
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
16 that the Network on Chip (NoC) probes detects are transported over the
25 const: samsung,exynos5420-nocp
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| /Documentation/devicetree/bindings/net/bluetooth/ |
| D | nxp,88w8987-bt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/nxp,88w8987-bt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This binding describes UART-attached NXP bluetooth chips. These chips
11 are dual-radio chips supporting WiFi and Bluetooth. The bluetooth
12 works on standard H4 protocol over 4-wire UART. The RTS and CTS lines
14 asserts break signal over UART-TX line to put the chip into power save
15 state. De-asserting break wakes up the BT chip.
18 - Neeraj Sanjay Kale <neeraj.sanjaykale@nxp.com>
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| /Documentation/devicetree/bindings/regulator/ |
| D | richtek,rt6245-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT6245 is a high-performance, synchronous step-down converter
18 - $ref: regulator.yaml#
23 - richtek,rt6245
28 enable-gpios:
30 A connection of the chip 'enable' gpio line. If not provided,
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| /Documentation/w1/masters/ |
| D | ds2490.rst | 13 -----------
15 The Maxim/Dallas Semiconductor DS2490 is a chip
16 which allows to build USB <-> W1 bridges.
18 DS9490(R) is a USB <-> W1 bus master device
19 which has 0x81 family ID integrated chip and DS2490
20 low-level operational chip.
24 - The weak pullup current is a minimum of 0.9mA and maximum of 6.0mA.
25 - The 5V strong pullup is supported with a minimum of 5.9mA and a
27 - The hardware will detect when devices are attached to the bus on the
31 - The number of USB bus transactions could be reduced if w1_reset_send
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,imx7ulp-sim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 The system integration module (SIM) provides system control and chip configuration
16 registers. In this module, chip revision information is located in JTAG ID register,
23 - const: fsl,imx7ulp-sim
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| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | amlogic,meson-gx-ao-secure.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
22 const: amlogic,meson-gx-ao-secure
24 - compatible
29 - items:
30 - const: amlogic,meson-gx-ao-secure
31 - const: syscon
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