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/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst36 # Clear error injections:
37 # clear clear all rx and tx error injections
38 # rx-clear clear all rx error injections
39 # tx-clear clear all tx error injections
40 # <op> clear clear all rx and tx error injections for <op>
41 # <op> rx-clear clear all rx error injections for <op>
42 # <op> tx-clear clear all tx error injections for <op>
78 clear
94 addition, there are commands to clear existing error injection commands and
131 Clear Error Injections
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/Documentation/ABI/testing/
Dsysfs-pps29 What: /sys/class/pps/ppsX/clear
33 The /sys/class/pps/ppsX/clear file reports the clear events
34 and the clear sequence number of the X-th source in the form:
38 If the source has no clear events the content of this file
Dsysfs-firmware-opal-sensor-groups12 What: /sys/firmware/opal/sensor_groups/<sensor_group_name>/clear
15 Description: Sysfs file to clear the min-max of all the sensors
18 Writing 1 to this file will clear the minimum and
Ddebugfs-cec-error-inj17 exception is that the command 'clear' without any arguments must be
21 This ensures that you can always do 'echo clear >error-inj' to clear any
Dsysfs-kernel-slab49 allocated using the fast path. It can be written to clear the
61 of partially used slabs. It can be written to clear the current
73 remote cpu frees. It can be written to clear the current count.
84 clear the current count.
96 clear the current count.
127 allocation from a certain node. It can be written to clear the
148 was deactivated. It can be written to clear the current count.
158 was deactivated. It can be written to clear the current count.
169 remotely. It can be written to clear the current count.
180 list. It can be written to clear the current count.
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Ddebugfs-hisi-zip16 Description: Compression/decompression core debug registers read clear
17 control. 1 means enable register read clear, otherwise 0.
19 disable counters clear after reading of these registers.
56 Description: QM debug registers(regs) read clear control. 1 means enable
57 register read clear, otherwise 0.
59 disable counters clear after reading of these registers.
Ddebugfs-cxl29 attribute, the memdev driver sends a clear poison command to
32 for 64 bytes starting at address. It is not an error to clear
34 device cannot clear poison from the address, -ENXIO is returned.
Ddebugfs-hisi-hpre17 Description: HPRE cores debug registers read clear control. 1 means enable
18 register read clear, otherwise 0. Writing to this file has no
19 functional effect, only enable or disable counters clear after
63 Description: QM debug registers(regs) read clear control. 1 means enable
64 register read clear, otherwise 0.
66 disable counters clear after reading of these registers.
Dsysfs-firmware-gsmi48 This file is used to clear out a portion/the
52 clear. Not all platforms support fractional
Drtc-cdev40 * RTC_VL_CLEAR: Clear the voltage status of the RTC. Some RTCs
42 replaced or charged to be able to clear the status.
/Documentation/driver-api/
Dpps.rst149 clear echo name power/ uevent
152 Inside each "assert" and "clear" file you can find the timestamp and a
190 source 0 - assert 1186592699.388832443, sequence: 364 - clear 0.000000000, sequence: 0
191 source 0 - assert 1186592700.388931295, sequence: 365 - clear 0.000000000, sequence: 0
192 source 0 - assert 1186592701.389032765, sequence: 366 - clear 0.000000000, sequence: 0
238 so it is used for PPS assert edge. PPS clear edge can be determined only
242 geared towards using the clear edge for time synchronization.
244 Clear edge polling is done with disabled interrupts so it's better to select
245 delay between assert and clear edge as small as possible to reduce system
246 latencies. But if it is too small slave won't be able to capture clear edge
/Documentation/devicetree/bindings/interrupt-controller/
Darm,versatile-fpga-irq.txt15 - clear-mask: a u32 number representing the mask written to clear all IRQs
31 clear-mask = <0xffffffff>;
/Documentation/userspace-api/media/v4l/
Dv4l2grab.c.rst33 #define CLEAR(x) memset(&(x), 0, sizeof(x))
75 CLEAR(fmt);
90 CLEAR(req);
98 CLEAR(buf);
118 CLEAR(buf);
143 CLEAR(buf);
Dcapture.c.rst35 #define CLEAR(x) memset(&(x), 0, sizeof(x))
110 CLEAR(buf);
139 CLEAR(buf);
247 CLEAR(buf);
264 CLEAR(buf);
327 CLEAR(req);
359 CLEAR(buf);
385 CLEAR(req);
466 CLEAR(cropcap);
489 CLEAR(fmt);
Dselection-api-vs-crop-api.rst15 selection API makes a clear distinction between composing and cropping
30 cropping/composing in a clear, intuitive and portable way. Next, with
/Documentation/translations/zh_CN/dev-tools/
Dkmemleak.rst36 # echo clear > /sys/kernel/debug/kmemleak
63 * clear
108 时编写的漏洞百出的代码导致的。为了解决这种情况你可以使用 'clear' 命令来清除
109 /sys/kernel/debug/kmemleak 输出的所有的未引用对象。在执行 'clear' 后执行 'scan'
114 # echo clear > /sys/kernel/debug/kmemleak
131 # echo clear > /sys/kernel/debug/kmemleak
/Documentation/dev-tools/
Dkmemleak.rst30 To clear the list of all current possible memory leaks::
32 # echo clear > /sys/kernel/debug/kmemleak
59 - clear
60 clear list of current memory leak suspects, done by
123 'clear' command to clear all reported unreferenced objects from the
124 /sys/kernel/debug/kmemleak output. By issuing a 'scan' after a 'clear'
130 # echo clear > /sys/kernel/debug/kmemleak
148 # echo clear > /sys/kernel/debug/kmemleak
/Documentation/arch/powerpc/
Ddexcr.rst90 - This aspect is clear / clear this aspect
96 - This aspect will be clear after exec / clear this aspect after exec
109 * The set/clear terminology refers to setting/clearing the bit in the DEXCR.
171 can still clear its own NPHIE aspect without privileges).
/Documentation/devicetree/bindings/iio/light/
Drohm,bu27008.yaml13 The ROHM BU27008 is a sensor with 5 photodiodes (red, green, blue, clear
15 available and two out of the rest three (blue, clear, IR) can be
Drohm,bu27010.yaml13 The ROHM BU27010 is a sensor with 6 photodiodes (red, green, blue, clear,
16 three (blue, clear, IR) can be selected to be simultaneously measured.
/Documentation/
Datomic_bitops.txt20 {set,clear,change}_bit()
25 test_and_{set,clear,change}_bit()
/Documentation/devicetree/bindings/gpio/
Dgpio-mmio.yaml15 of set/clear-bit registers. Such controllers are common for glue logic in
51 Register to CLEAR the value of the GPIO lines. Setting a bit in this
53 the SET register will be used to clear the GPIO lines as well, by
/Documentation/leds/
Dledtrig-oneshot.rst6 no clear trap points to put standard led-on and led-off settings. Using this
12 first case, the trigger produces a clear single controlled blink for each
/Documentation/admin-guide/hw-vuln/
Dtsx_async_abort.rst100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
107 instructions without a guarantee that they clear the CPU buffers.
114 * - 'Mitigation: Clear CPU buffers'
115 - The microcode has been updated to clear the buffers. TSX is still enabled.
157 system it will clear CPU buffers on ring transitions. On
206 tsx=on tsx_async_abort=full The system will use VERW to clear CPU
220 For unaffected platforms "tsx=on" and "tsx_async_abort=full" does not clear CPU
235 VERW is not guaranteed to clear buffers
/Documentation/admin-guide/mm/
Dsoft-dirty.rst8 1. Clear soft-dirty bits from the task's PTEs.
28 soft-dirty bits clear, the #PF-s that occur after that are processed fast.

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