Searched +full:clk +full:- +full:out +full:- +full:strength (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/net/ |
| D | qca,ar803x.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
27 description: Clock output driver strength.
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| D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | brcm,bcm4329-fmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arend van Spriel <arend@broadcom.com>
19 - $ref: ieee80211.yaml#
24 - items:
25 - enum:
26 - brcm,bcm43143-fmac
27 - brcm,bcm4341b0-fmac
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| /Documentation/driver-api/ |
| D | clk.rst | 2 The Common Clk Framework
7 This document endeavours to explain the common clk framework details,
9 detailed explanation of the clock api in include/linux/clk.h, but
15 The common clk framework is an interface to control the clock nodes
22 clk which unifies the framework-level accounting and infrastructure that
24 is a common implementation of the clk.h api, defined in
25 drivers/clk/clk.c. Finally there is struct clk_ops, whose operations
26 are invoked by the clk api implementation.
28 The second half of the interface is comprised of the hardware-specific
30 hardware-specific structures needed to model a particular clock. For
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| D | pin-control.rst | 9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
24 set drive strength, etc. for individual pins or groups of pins.
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
60 .. code-block:: c
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