| /Documentation/devicetree/bindings/clock/ |
| D | qcom,rpmhcc.yaml | 20 - qcom,qdu1000-rpmh-clk
21 - qcom,sa8775p-rpmh-clk
22 - qcom,sc7180-rpmh-clk
23 - qcom,sc7280-rpmh-clk
24 - qcom,sc8180x-rpmh-clk
25 - qcom,sc8280xp-rpmh-clk
26 - qcom,sdm670-rpmh-clk
27 - qcom,sdm845-rpmh-clk
28 - qcom,sdx55-rpmh-clk
29 - qcom,sdx65-rpmh-clk
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| D | allwinner,sun4i-a10-gates-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
30 - const: allwinner,sun6i-a31-ahb1-gates-clk
31 - const: allwinner,sun8i-a23-ahb1-gates-clk
32 - const: allwinner,sun9i-a80-ahb0-gates-clk
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| D | allwinner,sun4i-a10-usb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml#
27 - allwinner,sun4i-a10-usb-clk
28 - allwinner,sun5i-a13-usb-clk
29 - allwinner,sun6i-a31-usb-clk
30 - allwinner,sun8i-a23-usb-clk
31 - allwinner,sun8i-h3-usb-clk
58 const: allwinner,sun4i-a10-usb-clk
69 const: allwinner,sun5i-a13-usb-clk
80 const: allwinner,sun6i-a31-usb-clk
91 const: allwinner,sun8i-a23-usb-clk
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| D | sprd,sc9860-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
18 - sprd,sc9860-aonsecure-clk
23 - sprd,sc9860-ap-clk
24 - sprd,sc9860-cam-clk
26 - sprd,sc9860-disp-clk
28 - sprd,sc9860-gpu-clk
31 - sprd,sc9860-vsp-clk
67 - sprd,sc9860-gpu-clk
80 - sprd,sc9860-aonsecure-clk
81 - sprd,sc9860-cam-clk
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| D | allwinner,sun8i-a83t-de2-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml#
22 - const: allwinner,sun8i-a83t-de2-clk
23 - const: allwinner,sun8i-h3-de2-clk
24 - const: allwinner,sun8i-v3s-de2-clk
25 - const: allwinner,sun50i-a64-de2-clk
26 - const: allwinner,sun50i-h5-de2-clk
27 - const: allwinner,sun50i-h6-de3-clk
29 - const: allwinner,sun8i-r40-de2-clk
30 - const: allwinner,sun8i-h3-de2-clk
32 - const: allwinner,sun20i-d1-de2-clk
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| D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
45 clk@1c20000 {
47 compatible = "allwinner,sun4i-a10-pll1-clk";
54 clk@1c20000 {
56 compatible = "allwinner,sun6i-a31-pll1-clk";
63 clk@1c20000 {
65 compatible = "allwinner,sun8i-a23-pll1-clk";
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| D | allwinner,sun4i-a10-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
21 - allwinner,sun4i-a10-ahb-clk
22 - allwinner,sun6i-a31-ahb1-clk
23 - allwinner,sun8i-h3-ahb2-clk
51 const: allwinner,sun4i-a10-ahb-clk
62 const: allwinner,sun6i-a31-ahb1-clk
73 const: allwinner,sun8i-h3-ahb2-clk
84 compatible = "allwinner,sun4i-a10-ahb-clk";
93 compatible = "allwinner,sun6i-a31-ahb1-clk";
102 compatible = "allwinner,sun8i-h3-ahb2-clk";
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| D | allwinner,sun4i-a10-mod0-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml#
20 - allwinner,sun4i-a10-mod0-clk
21 - allwinner,sun9i-a80-mod0-clk
36 - allwinner,sun4i-a10-mod0-clk
37 - allwinner,sun9i-a80-mod0-clk
63 clk@1c20080 {
65 compatible = "allwinner,sun4i-a10-mod0-clk";
72 clk@8001454 {
74 compatible = "allwinner,sun4i-a10-mod0-clk";
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| D | nuvoton,npcm750-clk.txt | 22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
32 clk: clock-controller@f0801000 {
33 compatible = "nuvoton,npcm750-clk";
43 clk_refclk: clk-refclk {
51 clk_sysbypck: clk-sysbypck {
59 clk_mcbypck: clk-mcbypck {
67 clk_rg1refck: clk-rg1refck {
75 clk_rg2refck: clk-rg2refck {
82 clk_xin: clk-xin {
90 Example: GMAC controller node that consumes two clocks: a generated clk by the
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| D | fsl,scu-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
24 - fsl,imx8dxl-clk
25 - fsl,imx8qm-clk
26 - fsl,imx8qxp-clk
27 - const: fsl,scu-clk
41 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
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| D | allwinner,sun9i-a80-apb0-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
21 - allwinner,sun9i-a80-apb0-clk
22 - allwinner,sun9i-a80-apb1-clk
46 clk@6000070 {
48 compatible = "allwinner,sun9i-a80-apb0-clk";
55 clk@6000074 {
57 compatible = "allwinner,sun9i-a80-apb1-clk";
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml#
25 - allwinner,sun4i-a10-mmc-clk
26 - allwinner,sun9i-a80-mmc-clk
53 const: allwinner,sun4i-a10-mmc-clk
67 clk@1c20088 {
69 compatible = "allwinner,sun4i-a10-mmc-clk";
78 clk@6000410 {
80 compatible = "allwinner,sun9i-a80-mmc-clk";
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| D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
24 - allwinner,sun4i-a10-tcon-ch0-clk
25 - allwinner,sun4i-a10-tcon-ch1-clk
49 const: allwinner,sun4i-a10-tcon-ch0-clk
59 clk@1c20118 {
62 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
69 clk@1c2012c {
71 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
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| D | altr_socfpga.txt | 12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
24 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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| D | allwinner,sun4i-a10-mbus-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml#
21 - allwinner,sun5i-a13-mbus-clk
22 - allwinner,sun8i-a23-mbus-clk
46 clk@1c2015c {
48 compatible = "allwinner,sun5i-a13-mbus-clk";
55 clk@1c2015c {
57 compatible = "allwinner,sun8i-a23-mbus-clk";
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| D | loongson,ls2k-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml#
19 - loongson,ls2k0500-clk
20 - loongson,ls2k-clk # This is for Loongson-2K1000
21 - loongson,ls2k2000-clk
38 ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
59 clk: clock-controller@1fe00480 {
60 compatible = "loongson,ls2k-clk";
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| D | xlnx,versal-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
25 - xlnx,versal-net-clk
26 - const: xlnx,versal-clk
55 - xlnx,versal-clk
74 - xlnx,versal-net-clk
95 - xlnx,zynqmp-clk
131 compatible = "xlnx,versal-clk";
140 compatible = "xlnx,zynqmp-clk";
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| /Documentation/devicetree/bindings/clock/st/ |
| D | st,flexgen.txt | 88 clk_s_c0_flexgen: clk-s-c0-flexgen {
101 clock-output-names = "clk-icn-gpu",
102 "clk-fdma",
103 "clk-nand",
104 "clk-hva",
105 "clk-proc-stfe",
106 "clk-proc-tp",
107 "clk-rx-icn-dmu",
108 "clk-rx-icn-hva",
109 "clk-icn-cpu",
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| /Documentation/devicetree/bindings/mfd/ |
| D | allwinner,sun6i-a31-prcm.yaml | 23 "^.*-(clk|rst)$":
30 - allwinner,sun4i-a10-mod0-clk
31 - allwinner,sun6i-a31-apb0-clk
32 - allwinner,sun6i-a31-apb0-gates-clk
33 - allwinner,sun6i-a31-ar100-clk
54 const: allwinner,sun4i-a10-mod0-clk
76 const: allwinner,sun6i-a31-apb0-clk
98 const: allwinner,sun6i-a31-apb0-gates-clk
125 const: allwinner,sun6i-a31-ar100-clk
174 ar100: ar100-clk {
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| /Documentation/devicetree/bindings/soc/amlogic/ |
| D | amlogic,meson-gx-clk-measure.yaml | 4 $id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-clk-measure.yaml#
19 - amlogic,meson-gx-clk-measure
20 - amlogic,meson8-clk-measure
21 - amlogic,meson8b-clk-measure
22 - amlogic,meson-axg-clk-measure
23 - amlogic,meson-g12a-clk-measure
24 - amlogic,meson-sm1-clk-measure
38 compatible = "amlogic,meson-gx-clk-measure";
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx93-media-blk-ctrl.yaml | 67 clocks = <&clk IMX93_CLK_MEDIA_APB>,
68 <&clk IMX93_CLK_MEDIA_AXI>,
69 <&clk IMX93_CLK_NIC_MEDIA_GATE>,
70 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
71 <&clk IMX93_CLK_CAM_PIX>,
72 <&clk IMX93_CLK_PXP_GATE>,
73 <&clk IMX93_CLK_LCDIF_GATE>,
74 <&clk IMX93_CLK_ISI_GATE>,
75 <&clk IMX93_CLK_MIPI_CSI_GATE>,
76 <&clk IMX93_CLK_MIPI_DSI_GATE>;
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| D | fsl,imx8mn-disp-blk-ctrl.yaml | 82 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
83 <&clk IMX8MN_CLK_DISP_APB>,
84 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
85 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
86 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
87 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
88 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
89 <&clk IMX8MN_CLK_DSI_CORE>,
90 <&clk IMX8MN_CLK_DSI_PHY_REF>,
91 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
[all …]
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| D | fsl,imx8mm-disp-blk-ctrl.yaml | 80 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
81 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
82 <&clk IMX8MM_CLK_CSI1_ROOT>,
83 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
84 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
85 <&clk IMX8MM_CLK_DISP_ROOT>,
86 <&clk IMX8MM_CLK_DSI_CORE>,
87 <&clk IMX8MM_CLK_DSI_PHY_REF>,
88 <&clk IMX8MM_CLK_CSI1_CORE>,
89 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
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| /Documentation/dev-tools/kunit/api/ |
| D | clk.rst | 4 Clk API
7 The KUnit clk API is used to test clk providers and clk consumers.
9 .. kernel-doc:: drivers/clk/clk_kunit_helpers.c
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| /Documentation/devicetree/bindings/display/imx/ |
| D | nxp,imx8mq-dcss.yaml | 92 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
93 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
94 <&clk IMX8MQ_CLK_DISP_DTRC>;
96 assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
97 <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
98 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
99 <&clk IMX8MQ_CLK_27M>;
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