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/Documentation/devicetree/bindings/clock/
Dqcom,sc7280-lpasscorecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm LPASS core and audio clock control module provides the clocks and
17 include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
18 include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
23 clock-names: true
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Dqcom,gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm graphics clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,gpucc-sdm845.h
18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h
19 include/dt-bindings/clock/qcom,gpucc-sc7180.h
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Dmaxim,max77686.txt1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
3 This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4 multi-function device. More information can be found in MFD DT binding
6 bindings/mfd/max77686.txt for MAX77686 and
7 bindings/mfd/max77802.txt for MAX77802 and
8 bindings/mfd/max77620.txt for MAX77620.
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
12 dt-bindings/clock/maxim,max77686.h.
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
17 dt-bindings/clock/maxim,max77802.h.
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Dartpec6.txt1 * Clock bindings for Axis ARTPEC-6 chip
3 The bindings are based on the clock provider binding in
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 ----------------
9 There are two external inputs to the main clock controller which should be
10 provided using the common clock bindings.
11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference clock (optional).
14 Main clock controller
15 ---------------------
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Dqcom,sc7180-lpasscorecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core Clock Controller on SC7180
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm LPASS core clock control module provides the clocks and power
16 See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
21 - qcom,sc7180-lpasshm
22 - qcom,sc7180-lpasscorecc
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Dqcom,sm8450-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on SM8450
10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
14 Qualcomm camera clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,sc8280xp-camcc.h
19 include/dt-bindings/clock/qcom,sm8450-camcc.h
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Dqcom,sm8450-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm graphics clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,sm4450-gpucc.h
18 include/dt-bindings/clock/qcom,sm8450-gpucc.h
19 include/dt-bindings/clock/qcom,sm8550-gpucc.h
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Dsilabs,si514.txt1 Binding for Silicon Labs 514 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible: Shall be "silabs,si514"
13 - reg: I2C device address.
14 - #clock-cells: From common clock bindings: Shall be 0.
17 - clock-output-names: From common clock bindings. Recommended to be "si514".
20 si514: clock-generator@55 {
22 #clock-cells = <0>;
Dsilabs,si544.txt1 Binding for Silicon Labs 544 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
12 - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
14 - reg: I2C device address.
15 - #clock-cells: From common clock bindings: Shall be 0.
18 - clock-output-names: From common clock bindings. Recommended to be "si544".
21 si544: clock-controller@55 {
23 #clock-cells = <0>;
Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm video clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
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Dqcom,sm8550-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 Qualcomm display clock control module provides the clocks, resets and power
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
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Dhisi-crg.txt1 * HiSilicon Clock and Reset Generator(CRG)
3 The CRG module provides clock and reset signals to various
6 This binding uses the following bindings:
7 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 Documentation/devicetree/bindings/reset/reset.txt
12 - compatible: should be one of the following.
13 - "hisilicon,hi3516cv300-crg"
14 - "hisilicon,hi3516cv300-sysctrl"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
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Dmicrochip,pic32.txt1 Microchip PIC32 Clock Controller Binding
2 ----------------------------------------
3 Microchip clock controller is consists of few oscillators, PLL, multiplexer
6 This binding uses common clock bindings.
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible: shall be "microchip,pic32mzda-clk".
11 - reg: shall contain base address and length of clock registers.
12 - #clock-cells: shall be 1.
15 - microchip,pic32mzda-sosc: shall be added only if platform has
19 rootclk: clock-controller@1f801200 {
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Dst,stm32mp1-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32MP1 Reset Clock Controller
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
13 The RCC IP is both a reset and a clock controller.
17 This binding uses common clock bindings
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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Dmarvell,mmp2-audio-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 Audio Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The audio clock controller generates and supplies the clocks to the audio
16 Each clock is assigned an identifier and client nodes use this identifier
17 to specify the clock which they consume.
20 <dt-bindings/clock/marvell,mmp2-audio.h>.
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Drenesas,rzg2l-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
15 similar, but does not have Clock Monitor Registers.
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
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Dmarvell,berlin.txt1 Device Tree Clock bindings for Marvell Berlin
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 Clock related registers are spread among the chip control registers. Berlin
8 clock node should be a sub-node of the chip controller node. Marvell Berlin2
13 - compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
14 - #clock-cells: must be 1
15 - clocks: must be the input parent clock phandle
16 - clock-names: name of the input parent clock
17 Allowed clock-names for the reference clocks are
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Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
17 This level of clock gating is provided after the clocks are generated
18 by the SCU resources and clock controls. Thus even if the clock is
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Dmoxa,moxart-clock.txt1 Device Tree Clock bindings for arch-moxart
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - compatible : Must be "moxa,moxart-pll-clock"
15 - #clock-cells : Should be 0
16 - reg : Should contain registers location and length
17 - clocks : Should contain phandle + clock-specifier for the parent clock
20 - clock-output-names : Should contain clock name
26 - compatible : Must be "moxa,moxart-apb-clock"
27 - #clock-cells : Should be 0
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Dimg,boston-clock.txt1 Binding for Imagination Technologies MIPS Boston clock sources.
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11 - compatible : Should be "img,boston-clock".
12 - #clock-cells : Should be set to 1.
13 Values available for clock consumers can be found in the header file:
14 <dt-bindings/clock/boston-clock.h>
18 system-controller@17ffd000 {
19 compatible = "img,boston-platform-regs", "syscon";
22 clk_boston: clock {
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/Documentation/devicetree/bindings/clock/ti/
Dcomposite.txt1 Binding for TI composite clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped composite clock with multiple different sub-types;
6 a multiplexer clock with multiple input clock signals or parents, one
9 an adjustable clock rate divider, this behaves exactly as [3]
12 clock, this behaves exactly as [4]
15 merged to this clock. The component clocks shall be of one of the
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/mux.txt
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Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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/Documentation/devicetree/bindings/mfd/
Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
27 System controller Advanced Power Bus (APB) interface clock source.
29 clock-names:
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/Documentation/devicetree/bindings/clock/st/
Dst,clkgen.txt30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
41 - reg : A Base address and length of the register set.
45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32";
49 clk_s_a0_pll: clk-s-a0-pll {
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/Documentation/devicetree/bindings/display/armada/
Dmarvell,dove-lcd.txt1 Device Tree bindings for Armada DRM CRTC driver
4 - compatible: value should be "marvell,dove-lcd".
5 - reg: base address and size of the LCD controller
6 - interrupts: single interrupt number for the LCD controller
7 - port: video output port with endpoints, as described by graph.txt
11 - clocks: as described by clock-bindings.txt
12 - clock-names: as described by clock-bindings.txt
13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
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