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/Documentation/devicetree/bindings/clock/
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
Dmoxa,moxart-clock.txt1 Device Tree Clock bindings for arch-moxart
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - compatible : Must be "moxa,moxart-pll-clock"
15 - #clock-cells : Should be 0
16 - reg : Should contain registers location and length
17 - clocks : Should contain phandle + clock-specifier for the parent clock
20 - clock-output-names : Should contain clock name
26 - compatible : Must be "moxa,moxart-apb-clock"
27 - #clock-cells : Should be 0
[all …]
Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
[all …]
Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
[all …]
Dsamsung,exynos5410-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5410 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
[all …]
/Documentation/netlink/specs/
Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 name: dpll
8 -
10 name: mode
16 -
17 name: manual
20 -
21 name: automatic
23 render-max: true
24 -
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Duqe_serial.txt4 compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
5 "fsl,t1040-ucc-uart".
6 port-number : port number of UCC-UART
7 tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
8 should be "clk1"-"clk28" for external clock source.
13 compatible = "fsl,t1040-ucc-uart";
14 port-number = <0>;
15 rx-clock-name = "brg2";
16 tx-clock-name = "brg2";
Dfsl,ucc-hdlc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
12 - Frank Li <Frank.Li@nxp.com>
16 const: fsl,ucc-hdlc
24 cell-index:
27 rx-clock-name:
30 - pattern: "^brg([0-9]|1[0-6])$"
[all …]
/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
[all …]
/Documentation/devicetree/bindings/mfd/
Drockchip,rk808.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
20 - rockchip,rk808
28 '#clock-cells':
30 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
33 clock-output-names:
35 From common clock binding to override the default output clock name.
[all …]
Drockchip,rk805.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
20 - rockchip,rk805
28 '#clock-cells':
30 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
34 clock-output-names:
36 From common clock binding to override the default output clock name.
[all …]
Drohm,bd71828-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71828-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71828GW is a single-chip power management IC for battery-powered portable
15 single-cell linear charger. Also included is a Coulomb counter, a real-time
16 clock (RTC), and a 32.768 kHz clock gate.
21 - const: rohm,bd71828
23 - items:
[all …]
Dmaxim,max77686.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
18 current regulators, RTC and clock outputs.
20 The MAX77686 provides three 32.768khz clock outputs that can be controlled
21 (gated/ungated) over I2C. The clock IDs are defined as preprocessor macros
22 in dt-bindings/clock/maxim,max77686.h.
28 '#clock-cells':
[all …]
Drohm,bd71815-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71815-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71815AGW is a single-chip power management ICs for battery-powered
15 for LED and a 500 mA single-cell linear charger. Also included is a Coulomb
16 counter, a real-time clock (RTC), and a 32.768 kHz clock gate and two GPOs.
30 gpio-controller: true
32 "#gpio-cells":
[all …]
Drockchip,rk818.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
20 - rockchip,rk818
28 '#clock-cells':
30 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
33 clock-output-names:
35 From common clock binding to override the default output clock name.
[all …]
Drockchip,rk817.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
21 - rockchip,rk809
22 - rockchip,rk817
30 '#clock-cells':
32 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
39 clock-names:
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/Documentation/devicetree/bindings/regulator/
Dfixed-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: regulator.yaml#
21 - if:
25 const: regulator-fixed-clock
[all …]
/Documentation/devicetree/bindings/display/
Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
[all …]
/Documentation/devicetree/bindings/devfreq/event/
Dsamsung,exynos-ppmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
19 Exynos PPMU driver uses the devfreq-event class to provide event data to
26 - samsung,exynos-ppmu
27 - samsung,exynos-ppmu-v2
29 clock-names:
[all …]
/Documentation/ABI/testing/
Dconfigfs-usb-gadget-uac21 What: /config/usb-gadget/gadget/functions/uac2.name
9 c_srate list of capture sampling rates (comma-separated)
11 c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto)
24 p_srate list of playback sampling rates (comma-separated)
26 p_hs_bint playback bInterval for HS/SS (1-4: fixed, 0: auto)
35 req_number the number of pre-allocated requests
37 function_name name of the interface
38 if_ctrl_name topology control name
39 clksrc_in_name input clock name
40 clksrc_out_name output clock name
[all …]
/Documentation/sound/cards/
Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
[all …]
/Documentation/devicetree/bindings/sound/
Dnvidia,tegra186-dspk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
21 - $ref: dai-common.yaml#
25 pattern: "^dspk@[0-9a-f]*$"
[all …]
/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
19 "ssi_ssr_fck": The OMAP clock of that name
[all …]

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