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/Documentation/devicetree/bindings/clock/
Dxlnx,clocking-wizard.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
7 title: Xilinx clocking wizard
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
70 compatible = "xlnx,clocking-wizard";
Dmediatek,mt8186-fhctl.yaml7 title: MediaTek frequency hopping and spread spectrum clocking control
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
35 description: The percentage of spread spectrum clocking for one PLL.
Dmicrochip,mpfs-ccc.yaml15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
/Documentation/sound/soc/
Dclocking.rst2 Audio Clocking
5 This text describes the audio clocking terms in ASoC and digital audio in
6 general. Note: Audio clocking can be complex!
Dindex.rst17 clocking
/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
63 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
/Documentation/devicetree/bindings/serial/
Darm,mps2-uart.txt8 Required clocking property:
/Documentation/devicetree/bindings/misc/
Dlwn-bk4.txt17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
/Documentation/devicetree/bindings/i2c/
Di2c-mpc.yaml38 fsl,preserve-clocking:
86 fsl,preserve-clocking;
/Documentation/devicetree/bindings/timer/
Darm,mps2-timer.txt10 Required clocking property, have to be one of:
/Documentation/devicetree/bindings/watchdog/
Dnuvoton,npcm-wdt.txt15 Required clocking property, have to be one of:
/Documentation/devicetree/bindings/net/
Dintel,ixp4xx-hss.yaml105 use internal clocking as opposed to external clocking
/Documentation/devicetree/bindings/hwmon/
Dcirrus,lochnagar.yaml17 Audio system topology, clocking and power can all be controlled through
/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-audio.yaml23 Clocking setup for j721e:
32 Clocking setup for j7200:
Dcirrus,lochnagar.yaml17 Audio system topology, clocking and power can all be controlled through
Dti,j721e-cpb-ivi-audio.yaml30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
/Documentation/admin-guide/pm/
Dcpufreq_drivers.rst94 Processor Clocking Control Driver
113 Processor Clocking Control (PCC) is an interface between the platform
129 https://acpica.org/sites/acpica/files/Processor-Clocking-Control-v1p0.pdf
184 * assumes responsibility for managing the hardware clocking controls in order
/Documentation/devicetree/bindings/net/wireless/
Dti,wl1251.txt9 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
/Documentation/devicetree/bindings/spi/
Dnvidia,tegra20-sflash.yaml46 description: Maximum SPI clocking speed of the controller in Hz.
Dnvidia,tegra20-slink.yaml55 description: Maximum SPI clocking speed of the controller in Hz.
Dti,qspi.yaml64 description: Maximum SPI clocking speed of the controller in Hz.
Dnvidia,tegra114-spi.yaml56 description: Maximum SPI clocking speed of the controller in Hz.
/Documentation/peci/
Dpeci.rst27 PECI Wire interface uses a single wire for self-clocking and data
/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx93-media-blk-ctrl.yaml15 clocking, reset, and miscellaneous top-level controls for peripherals
/Documentation/driver-api/
Dslimbus.rst36 Framer device is responsible for clocking the bus, and transmitting frame-sync
49 responsible to select the active-framer for clocking the bus.

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