Home
last modified time | relevance | path

Searched full:clocks (Results 1 – 25 of 1964) sorted by relevance

12345678910>>...79

/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
20 All available clocks are defined as preprocessor macros in
26 # CMU_TOP which generates clocks for
28 # clocks
30 # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
34 # CMU_PERIC which generates clocks for
37 # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
[all …]
Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
[all …]
Drenesas,cpg-mstp-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
28 - renesas,r8a7779-mstp-clocks # R-Car H1
[all …]
Dsamsung,exynos5260-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
24 Phy clocks::
25 There are several clocks which are generated by specific PHYs. These clocks
27 These clocks are defined as fixed clocks in the driver with following names::
44 All available clocks are defined as preprocessor macros in
64 clocks:
91 clocks:
102 - clocks
111 clocks:
131 - clocks
[all …]
Dbrcm,bcm63xx-clocks.txt5 "brcm,bcm3368-clocks"
6 "brcm,bcm6318-clocks"
7 "brcm,bcm6318-ubus-clocks"
8 "brcm,bcm6328-clocks"
9 "brcm,bcm6358-clocks"
10 "brcm,bcm6362-clocks"
11 "brcm,bcm6368-clocks"
12 "brcm,bcm63268-clocks"
21 compatible = "brcm,bcm6328-clocks";
Dsamsung,exynos7-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
20 All available clocks are defined as preprocessor macros in
38 clocks:
65 clocks:
78 - clocks
87 clocks:
99 - clocks
108 clocks:
117 - clocks
126 clocks:
[all …]
Dvf610-clock.txt9 - clocks: list of clock identifiers which are external input clocks to the
11 the input clocks for a given controller.
12 - clock-names: list of names of clocks which are external input clocks to the
15 Input clocks for top clock controller:
22 ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
31 clocks = <&sxosc>, <&fxosc>;
39 clocks = <&clks VF610_CLK_UART1>;
Dsamsung,exynos850-clock.yaml18 clocks for different domains. Those CMU units are modeled as separate device
19 tree nodes, and might depend on each other. Root clocks in that clock tree are
20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
21 clocks must be defined as fixed-rate clocks in dts.
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
27 to specify the clock which they consume. All clocks available for usage
48 clocks:
71 clocks:
87 clocks:
[all …]
Dlpc1850-creg-clk.txt1 * NXP LPC1850 CREG clocks
4 control registers for two low speed clocks. One of the clocks is a
8 These clocks are used by the RTC and the Event Router peripherals.
20 - clocks:
25 The following clocks are available from the clock node.
39 clocks = <&xtal32>;
48 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
Dsamsung,exynosautov9-clock.yaml18 clocks for different domains. Those CMU units are modeled as separate device
19 tree nodes, and might depend on each other. Root clocks in that clock tree are
20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other clocks of function blocks (other CMUs) are usually
28 to specify the clock which they consume. All clocks available for usage
46 clocks:
69 clocks:
85 clocks:
103 clocks:
[all …]
Dbrcm,bcm2835-cprman.txt1 Broadcom BCM2835 CPRMAN clocks
6 The CPRMAN clock controller generates clocks in the audio power domain
21 - clocks: phandles to the parent clocks used as input to the module, in
32 Only external oscillator is required. The DSI clocks may
46 clocks: cprman@7e101000 {
50 clocks = <&clk_osc>;
57 clocks = <&clocks BCM2835_CLOCK_VPU>;
Dvt8500.txt15 Required properties for PLL clocks:
17 - clocks : shall be the input parent clock phandle for the clock. This should
21 Required properties for device clocks:
22 - clocks : shall be the input parent clock phandle for the clock. This should
27 Device Clocks
29 Device clocks are required to have one or both of the following sets of
33 Gated device clocks:
41 Divisor device clocks:
62 clocks = <&ref25>;
69 clocks = <&pllb>;
Dsamsung,exynosautov920-clock.yaml17 clocks for different domains. Those CMU units are modeled as separate device
18 tree nodes, and might depend on each other. Root clocks in that clock tree are
19 two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
22 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 dividers; all other clocks of function blocks (other CMUs) are usually
27 to specify the clock which they consume. All clocks available for usage
41 clocks:
64 clocks:
82 clocks:
103 clocks:
[all …]
Dstericsson,u8500-clks.yaml7 title: ST-Ericsson DB8500 (U8500) clocks
13 description: While named "U8500 clocks" these clocks are inside the
15 DB8520. These bindings consider the clocks present in the SoC
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
18 control management unit) clocks and PRCC (peripheral reset and
19 clock controller) clocks. For some reason PRCC 4 does not exist so
39 management unit) clocks. The cell indicates which PRCMU clock in the
51 reset and clock controller) peripheral clocks. The first cell indicates
65 and clock controller) kernel clocks. The first cell indicates which PRCC
[all …]
Dlpc1850-ccu.txt5 branch clocks are distributed between CCU1 and CCU2.
21 - clocks:
22 Shall contain a list of phandles for the base clocks routed
23 from the CGU to the specific CCU. See mapping of base clocks
35 Which branch clocks that are available on the CCU depends on the
38 A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
71 /* A user of CCU branch clocks */
74 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
Dpistachio-clock.txt8 External clocks:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
37 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
57 - clocks: Must contain an entry for each clock in clock-names.
65 clocks = <&clk_core CLK_PERIPH_SYS>;
74 The peripheral general control block generates system interface clocks and
85 - clocks: Must contain an entry for each clock in clock-names.
[all …]
Dst,stm32-rcc.txt19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
21 between gated clocks and other clocks and an index specifying the clock to
23 - clocks: External oscillator clock phandle
34 clocks = <&clk_hse>, <&clk_i2s_ckin>;
37 Specifying gated clocks
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
67 Specifying other clocks
84 9 CLK_I2S (I2S clocks)
85 10 CLK_SAI1 (audio clocks)
[all …]
/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]
/Documentation/devicetree/bindings/clock/ti/davinci/
Dda8xx-cfgchip.txt1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
5 gates. This document describes the bindings for those clocks.
10 USB PHY clocks
13 - compatible: shall be "ti,da830-usb-phy-clocks".
15 - clocks: phandles to the parent clocks corresponding to clock-names
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
26 - clocks: phandle to the parent clock
34 - clocks: phandle to the parent clock
42 - clocks: phandles to the parent clocks corresponding to clock-names
50 - clocks: phandles to the parent clocks corresponding to clock-names
[all …]
/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt5 functional clock but can be configured to provide different clocks.
9 In order to provide the support for ATL and its output clocks (which can be used
14 To be able to integrate the ATL clocks with DT clock tree.
15 Provides ccf level representation of the ATL clocks to be used by drivers.
25 - clocks : link phandles to functional clock of ATL
34 - ti,provided-clocks : List of phandles to the clocks associated with the ATL
35 - clocks : link phandles to functional clock of ATL
50 /* clock bindings for atl provided clocks */
54 clocks = <&atl_gfclk_mux>;
60 clocks = <&atl_gfclk_mux>;
[all …]
/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml26 clocks:
83 clocks:
95 assigned-clocks:
102 - clocks
104 - assigned-clocks
121 clocks:
131 assigned-clocks:
138 - clocks
140 - assigned-clocks
151 clocks:
[all …]
/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
17 assigned clocks
18 - clock-names: names of 3 leaf clocks used by audio ports
33 clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
/Documentation/devicetree/bindings/media/
Dst,stih4xx.txt9 - clocks: from common clock binding: handle hardware IP needed clocks, the
10 number of clocks may depend on the SoC type.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: names of the clocks listed in clocks property in the same order.
21 clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
Dst,st-delta.txt5 - clocks: from common clock binding: handle hardware IP needed clocks, the
6 number of clocks may depend on the SoC type.
8 - clock-names: names of the clocks listed in clocks property in the same order.
14 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
Dst,st-hva.txt10 - clocks: from common clock binding: handle hardware IP needed clocks, the
11 number of clocks may depend on the SoC type.
13 - clock-names: names of the clocks listed in clocks property in the same order.
23 clocks = <&clk_s_c0_flexgen CLK_HVA>;

12345678910>>...79