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/Documentation/devicetree/bindings/timer/
Djcore,pit.txt1 J-Core Programmable Interval Timer and Clocksource
7 - reg: Memory region(s) for timer/clocksource registers. For SMP,
Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
Dsnps,archs-gfrc.txt2 - clocksource provider for SMP SoC
Dsnps,archs-rtc.txt2 - clocksource provider for UP SoC
Dsnps,arc-timer.txt6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
Dimg,pistachio-gptimer.txt1 * Pistachio general-purpose timer based clocksource
Dloongson,ls1x-pwmtimer.yaml41 clocksource: timer@1fe5c030 {
Dingenic,sysost.yaml13 The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource
Drealtek,otto-timer.yaml11 as a per CPU clock event generator and an overall CPU clocksource.
/Documentation/devicetree/bindings/rtc/
Drtc-st-lpc.txt4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
/Documentation/virt/hyperv/
Dclocks.rst10 clocksource and clockevents via the standard arm_arch_timer.c
53 available, it prefers to use Linux's standard TSC-based clocksource.
54 Otherwise, it uses the clocksource for the Hyper-V synthetic system
82 drivers/clocksource/hyperv_timer.c.
/Documentation/devicetree/bindings/cpufreq/
Dnvidia,tegra124-cpufreq.txt12 - pll_x: Fast PLL clocksource.
14 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
/Documentation/devicetree/bindings/watchdog/
Dst_lpc_wdt.txt4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
/Documentation/translations/zh_CN/arch/mips/
Dingenic-tcu.rst62 定时器 drivers/clocksource/ingenic-timer.c
63 OST drivers/clocksource/ingenic-ost.c
/Documentation/translations/zh_TW/arch/mips/
Dingenic-tcu.rst62 定時器 drivers/clocksource/ingenic-timer.c
63 OST drivers/clocksource/ingenic-ost.c
/Documentation/arch/mips/
Dingenic-tcu.rst60 timers drivers/clocksource/ingenic-timer.c
61 OST drivers/clocksource/ingenic-ost.c
/Documentation/devicetree/bindings/pwm/
Dpwm-samsung.yaml19 Be aware that the clocksource driver supports only uniprocessor systems.
73 use PWM clocksource.
/Documentation/core-api/
Dtimekeeping.rst56 clocksource without (NTP) adjustments for clock drift. This is
130 clocksource.
140 while we are entering suspend with the clocksource powered down.
/Documentation/devicetree/bindings/soc/xilinx/
Dxlnx,vcu.txt16 - clocks: phandle for aclk and pll_ref clocksource
/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt1 NVIDIA Tegra124 DFLL FCPU clocksource
6 The DFLL IP block on Tegra is a root clocksource designed for clocking
/Documentation/timers/
Dtimekeeping.rst7 drivers/clocksource in the kernel tree, but the code may be spread out
61 ns ~= (clocksource * mult) >> shift
/Documentation/translations/zh_CN/userspace-api/
Dseccomp_filter.rst268 ``/sys/devices/system/clocksource/clocksource0/current_clocksource`` 设置为
/Documentation/virt/kvm/x86/
Dhypercalls.rst137 Returns KVM_EOPNOTSUPP if the host does not use TSC clocksource,
/Documentation/devicetree/bindings/display/msm/
Dgpu.yaml209 description: GPUCC clocksource clock
/Documentation/power/regulator/
Dconsumer.rst202 - clocksource with a voltage-controlled oscillator and control logic to change

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