Searched full:coherency (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | coherency-fabric.txt | 1 Coherency fabric
9 * "marvell,coherency-fabric", to be used for the coherency fabric of
12 * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
15 * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
18 - reg: Should contain coherency fabric registers location and
21 * For "marvell,coherency-fabric", the first pair for the coherency
24 * For "marvell,armada-375-coherency-fabric", only one pair is needed
27 * For "marvell,armada-380-coherency-fabric", only one pair is needed
37 coherency-fabric@d0020200 {
38 compatible = "marvell,coherency-fabric";
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | ccf.txt | 1 Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
5 The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
11 fsl,corenet1-cf - CoreNet coherency fabric version 1.
14 fsl,corenet2-cf - CoreNet coherency fabric version 2.
31 Specifies the number of Coherency Subdomain ID Port Mapping
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| D | cpus.txt | 27 Definition: The Coherency Subdomain ID Port Mapping Registers and
29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
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| D | mcm.txt | 2 MPX LAW & Coherency Module Device Tree Binding
35 MPX Coherency Module Node
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| D | ecm.txt | 2 E500 LAW & Coherency Module Device Tree Binding
35 E500 Coherency Module Node
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| D | pamu.txt | 36 The Coherency Subdomain ID Port Mapping Registers and
38 CoreNet Coherency fabric (CCF), provide a CoreNet
39 Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
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| /Documentation/filesystems/caching/ |
| D | netfs-api.rst | 18 (4) Cookies have coherency data that allows a cache to determine if the
35 (7) Data file coherency
72 for the cookie in the background, to check its coherency and, if necessary, to
104 and notes the coherency data.
116 The specified coherency data is stored in the cookie and will be matched
117 against coherency data stored on disk. The data pointer may be NULL if no data
118 is provided. If the coherency data doesn't match, the entire cache volume will
136 coherency data will be set to the value supplied. The amount of coherency data
163 The caller should also pass in a piece of coherency data in aux_data. A buffer
164 of size aux_data_len will be allocated and the coherency data copied in. It is
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| D | backend-api.rst | 147 u8 coherency[];
165 * ``coherency`` - A piece of coherency data that should be checked when the
168 * ``coherency_len`` - The amount of data in the coherency buffer.
203 * FSCACHE_COOKIE_NEEDS_UPDATE - The coherency data and/or object size has
227 * ``aux_len`` - The length of the coherency data buffer.
237 Each cookie also has a buffer for coherency data. This may also be inline or
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| /Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 6 cluster setup and teardown operations and to manage hardware coherency
33 mechanisms like Linux spinlocks may rely on coherency mechanisms which
73 enabling coherency.
83 coherency exit.
160 A CPU cannot start participating in hardware coherency until the
178 start participating in local coherency.
201 While in this state, the CPU exits coherency, including any
318 enabling of hardware coherency at the cluster level and any
323 setup to enable other CPUs in the cluster to enter coherency
329 cluster-level setup and hardware coherency complete
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| D | vlocks.rst | 151 guarantees coherency between overlapping memory accesses of
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| /Documentation/ABI/removed/ |
| D | net_dma | 7 coherency issues of the cpu potentially touching the buffers
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| /Documentation/devicetree/bindings/ufs/ |
| D | samsung,exynos-ufs.yaml | 69 - description: offset of the control register for UFS io coherency setting
71 Phandle and offset to the FSYSx sysreg for UFS io coherency setting.
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| /Documentation/filesystems/ |
| D | ocfs2.rst | 106 coherency=full (*) Disallow concurrent O_DIRECT writes, cluster inode
108 therefore full cluster coherency is guaranteed even
110 coherency=buffered Allow concurrent O_DIRECT writes without EX lock among
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| /Documentation/devicetree/bindings/watchdog/ |
| D | marvel.txt | 29 "nbclk" (L2/coherency fabric clock),
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| /Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 22 "nbclk" (L2/coherency fabric clock),
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
15 and manage coherency, TLB invalidations and memory barriers.
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| /Documentation/devicetree/bindings/pci/ |
| D | layerscape-pcie-gen4.txt | 20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
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| D | ti,j721e-pci-ep.yaml | 57 description: Indicates that the PCIe IP block can ensure the coherency
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| /Documentation/admin-guide/device-mapper/ |
| D | cache.rst | 98 worry about coherency. Coherency that exists is maintained, although
99 the cache will gradually cool as writes take place. If the coherency of
212 passthrough a degraded mode useful for various cache coherency
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| D | era.rst | 16 coherency after rolling back a vendor snapshot.
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| /Documentation/devicetree/bindings/cache/ |
| D | sifive,ccache0.yaml | 16 acts as directory-based coherency manager.
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| /Documentation/arch/arm64/ |
| D | booting.rst | 197 - Coherency
199 All CPUs to be booted by the kernel must be part of the same coherency
437 timers, coherency and system registers apply to all CPUs. All CPUs must
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| /Documentation/gpu/ |
| D | drm-mm.rst | 313 Memory Coherency
321 flushing of various kinds. This core CPU<->GPU coherency management is
324 object into the desired coherency domain (note that the object may be
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| /Documentation/core-api/ |
| D | cachetlb.rst | 343 Any necessary cache flushing or other coherency operations
380 coherency. It must do this by flushing the vmap range before doing
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| /Documentation/driver-api/cxl/ |
| D | maturity-map.rst | 157 * [0] Software managed coherency shared memory
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