Searched full:complete (Results 1 – 25 of 462) sorted by relevance
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| /Documentation/scheduler/ |
| D | completion.rst | 17 calls and complete() instead.
40 - the signaling side through a call to complete() or complete_all().
65 complete(&early_console_added);
68 'complete' is not helpful unless the purpose is super obvious...
76 to prevent races with asynchronous complete() calls from occurring.
80 does not happen until all related activities (complete() or reinit_completion())
127 _killable() and _interruptible()) variants, the wait might complete
130 stack and cause subtle data corruption if a complete() is done in some
136 or has a lock or other synchronization mechanism to make sure complete()
160 wait_for_completion(&setup_done); complete(&setup_done);
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| /Documentation/translations/zh_CN/scheduler/ |
| D | completion.rst | 66 complete(&early_console_added);
68 好的、直观的命名（一如既往地）有助于代码的可读性。将一个完成命名为 ``complete``
79 时应特别小心，因为必须保证在所有相关活动（complete()或reinit_completion()）发生
147 wait_for_completion(&setup_done); complete(setup_done);
221 void complete(struct completion *done)
232 简单地增加已完成的字段。但多次调用complete_all()是一个错误。complete()和
235 在任何时候，只能有一个线程在一个特定的 “struct completion”上调用 complete() 或
236 complete_all() - 通过等待队列自旋锁进行序列化。任何对 complete() 或
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| /Documentation/ABI/testing/ |
| D | sysfs-class-scsi_tape | 17 to and from the tape drive to complete. This includes all
24 to complete subtract read_ns and write_ns from this value.
65 read I/O requests to complete.
96 write I/O requests to complete.
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| D | debugfs-scmi-raw | 6 a complete SCMI synchronous command message (header included)
21 a complete SCMI asynchronous command message (header included)
73 a complete SCMI synchronous command message (header included)
97 a complete SCMI asynchronous command message (header included)
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| D | sysfs-class-fpga-manager | 34 * write complete = Doing post programming steps
35 * write complete error = Error while doing post programming
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| D | sysfs-firmware-dmi-tables | 21 The complete DMI information can be obtained using these two
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| D | sysfs-class-firmware | 8 image write is complete, echo 0 to the loading sysfs file. This
45 file to indicate that the write is complete. For firmware
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| D | sysfs-bus-dfl-devices-emif | 14 this memory interface. "1" for initialization complete, "0"
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| /Documentation/userspace-api/media/dvb/ |
| D | frontend-stat-properties.rst | 64 measurement was not complete yet.
83 measurement was not complete yet.
114 measurement was not complete yet.
142 measurement was not complete yet.
171 measurement was not complete yet.
199 measurement was not complete yet.
220 measurement was not complete yet.
242 measurement was not complete yet.
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| /Documentation/driver-api/dmaengine/ |
| D | client.rst | 318 stopped or until any running complete callbacks have finished. But it is
320 within a complete callback. dmaengine_synchronize() must be called before it
322 accessed from within the complete callback.
325 complete callbacks to finish before it returns. But the function must not be
326 called from atomic context or from within a complete callback.
347 4. Check Txn complete
355 the documentation in include/linux/dmaengine.h for a more complete
379 wait for the transfer and any running complete callbacks to finish before it
384 submitted descriptors or to free any resources accessed within the complete
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma3.yaml | 91 -bit 12-13: The transfer complete event mode
92 0x0: at block level, transfer complete event is generated at the end
94 0x2: at LLI level, the transfer complete event is generated at the end
97 0x3: at channel level, the transfer complete event is generated at the
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| /Documentation/userspace-api/media/drivers/ |
| D | npcm-video.rst | 21 - COMPLETE mode:
23 Capture the next complete frame into memory.
33 - ``V4L2_NPCM_CAPTURE_MODE_COMPLETE``: will set VCD to COMPLETE mode.
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| /Documentation/gpu/ |
| D | drm-vm-bind-async.rst | 28 signals these when the bind operation is complete.
44 current stipulated dma-fence maximum signal delay to complete and
58 assumed, where it matters, to complete in order of submission. No such
71 With Synchronous VM_BIND, the VM_BIND operations all complete before the
92 matters, to complete in order.
120 complete and signal the out_fence. In particular if the operation is
127 complete in the order they were submitted, but that is not the case
151 example due to lack of resources to complete and due to interrupted
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| /Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 119 CPU setup complete policy decision
127 policy decision CPU teardown complete
208 local CPU teardown complete
329 cluster-level setup and hardware coherency complete
336 Cluster-level setup is complete and hardware coherency is
354 Cluster-level setup is complete and hardware coherency is
430 coherency complete
469 initialisation: any other CPUs must wait for this to complete before
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| /Documentation/virt/acrn/ |
| D | io-request.rst | 74 FREE -> PENDING -> PROCESSING -> COMPLETE -> FREE -> ...
79 - COMPLETE: the I/O request has been processed
81 An I/O request in COMPLETE or FREE state is owned by the hypervisor. HSM and
96 f. The HSM updates I/O requests states to COMPLETE and notifies the hypervisor
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| /Documentation/admin-guide/device-mapper/ |
| D | statistics.rst | 82 that took 0-10 ms to complete, b is the number of requests
83 that took 10-20 ms to complete, c is the number of requests
84 that took 20-30 ms to complete and d is the number of
85 requests that took more than 30 ms to complete.
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| /Documentation/RCU/ |
| D | rcubarrier.rst | 41 grace period to elapse, it does not wait for the callbacks to complete.
56 outstanding RCU callbacks to complete. Please note that rcu_barrier()
158 for any pre-existing callbacks to complete.
175 RCU callbacks to complete.
205 10 complete(&rcu_barrier_completion);
260 4 complete(&rcu_barrier_completion);
364 state) before the grace period can complete. However, this is
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| /Documentation/driver-api/pm/ |
| D | notifiers.rst | 16 ``->resume()`` or even ``->prepare()`` and ``->complete()`` callbacks are not
21 from their ``->resume()`` or ``->complete()`` callback routines (user land
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| D | devices.rst | 344 the ``->complete`` callback will be the next one invoked after the
348 Note that this direct-complete procedure applies even if the device is
360 these flags is set, the PM core will not apply the direct-complete
386 issuing the ``->complete`` callback).
428 ``resume_noirq``, ``resume_early``, ``resume``, ``complete``.
452 4. The ``complete`` phase should undo the actions of the ``prepare`` phase.
454 ``complete`` phase the device hierarchy is traversed bottom-up.
458 until the ``complete`` phase runs.
465 skipped). In that case, the ``->complete`` callback is entirely
469 the case, the ``->complete`` callback can consult the device's
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| /Documentation/devicetree/bindings/perf/ |
| D | arm,ni.yaml | 18 - description: Complete configuration register space
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| /Documentation/admin-guide/media/ |
| D | bt8xx.rst | 21 Please see Documentation/admin-guide/media/bttv-cardlist.rst for a complete
108 For bug reports please send in a complete log with verbose=4 activated.
114 See Documentation/admin-guide/media/bttv-cardlist.rst for a complete list of
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| /Documentation/admin-guide/RAS/ |
| D | address-translation.rst | 11 I/O, etc., may not have a complete view of the system physical memory map.
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| /Documentation/admin-guide/aoe/ |
| D | status.sh | 4 # A more complete version of this script is aoe-stat, in the
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| /Documentation/arch/arm/stm32/ |
| D | stm32-dma-mdma-chaining.rst | 58 channel is null. The channel transfer complete of the last node is the end of
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
74 | | | complete | |
133 * the address of the STM32 DMA register to clear the Transfer Complete
135 * the mask of the Transfer Complete interrupt flag of the STM32 DMA channel.
207 Transfer Complete flag passed through
302 channel Transfer Complete flag mask.
390 Complete signal, triggering the STM32 MDMA channel), but the first data read
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| /Documentation/iio/ |
| D | iio_tools.rst | 24 yet complete programming interface that can be used for advanced projects.
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