Searched +full:controller +full:- +full:specific (Results 1 – 25 of 526) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
11 They could be common properties like reg or they could be controller
12 specific like delay in clock or data lines, etc. These properties need
13 to be defined in the peripheral node because they are per-peripheral
14 and there can be multiple peripherals attached to a controller. All
15 those properties are listed here. The controller specific properties
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| /Documentation/devicetree/bindings/mmc/ |
| D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
2 Mobile Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
22 compatible = "mellanox,bluefield-dw-mshc";
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| D | k3-dw-mshc.txt | 1 * Hisilicon specific extensions to the Synopsys Designware Mobile
2 Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
10 extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
17 with hi3670 specific extensions.
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
33 controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
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| D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
15 I/O space utilized by the controller. The size should
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
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| D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
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| /Documentation/devicetree/bindings/display/hisilicon/ |
| D | dw-dsi.txt | 1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
17 A example of HiKey board hi6220 SoC and board specific DT entry:
20 SoC specific:
22 compatible = "hisilicon,hi6220-dsi";
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| /Documentation/devicetree/bindings/input/ |
| D | brcm,bcm-keypad.txt | 1 * Broadcom Keypad Controller device tree bindings
3 Broadcom Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be "brcm,bcm-keypad"
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
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| D | omap-keypad.txt | 1 * TI's Keypad Controller device tree bindings
3 TI's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be one of the following
16 - "ti,omap4-keypad": For controllers compatible with omap4 keypad
17 controller.
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| /Documentation/devicetree/bindings/usb/ |
| D | omap-usb.txt | 1 OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12 interface between the controller and the phy. It should be "0" or "1"
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| D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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| /Documentation/devicetree/bindings/mfd/ |
| D | syscon-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/syscon-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Controller Registers R/W Common Properties
10 System controller node represents a register region containing a set
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
15 search using a specific compatible value), interrogate the node (or
20 - Lee Jones <lee@kernel.org>
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-hibvt.txt | 1 Hisilicon PWM controller
4 -compatible: should contain one SoC specific compatible string
5 The SoC specific strings supported including:
6 "hisilicon,hi3516cv300-pwm"
7 "hisilicon,hi3519v100-pwm"
8 "hisilicon,hi3559v100-shub-pwm"
9 "hisilicon,hi3559v100-pwm
10 - reg: physical base address and length of the controller's registers.
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - resets: phandle and reset specifier for the PWM controller reset.
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| /Documentation/ABI/testing/ |
| D | sysfs-class-led-flash | 55 Flash faults are re-read after strobing the flash. Possible
58 * led-over-voltage
59 flash controller voltage to the flash LED
60 has exceeded the limit specific to the flash controller
61 * flash-timeout-exceeded
65 * controller-over-temperature
66 the flash controller has
68 * controller-short-circuit
70 of the flash controller has been triggered
71 * led-power-supply-over-current
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-dsp-keystone.txt | 1 Keystone 2 DSP GPIO controller bindings
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
8 - 8 for C66x CorePacx CPUs 0-7
10 Keystone 2 DSP GPIO controller has specific features:
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
19 access device state control registers and the offset of device's specific
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx-pinctrl.txt | 1 * Freescale IOMUX Controller (IOMUXC) for i.MX
3 The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
20 Required properties for iomux controller:
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
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| D | pinctrl-sirf.txt | 1 CSR SiRFprimaII pinmux controller
4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Controller Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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| /Documentation/scsi/ |
| D | hpsa.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 HPSA - Hewlett Packard Smart Array driver
12 "split-brained" design of the cciss driver is a source of excess
19 - Smart Array P212
20 - Smart Array P410
21 - Smart Array P410i
22 - Smart Array P411
23 - Smart Array P812
24 - Smart Array P712m
25 - Smart Array P711m
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
15 properties are listed here. The controller specific properties should go in
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| /Documentation/devicetree/bindings/nvmem/ |
| D | microchip,lan9662-otpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN9662 OTP Controller (OTPC)
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
15 user specific data could be stored.
18 - $ref: nvmem.yaml#
23 - items:
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
17 search using a specific compatible value), interrogate the node (or
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-ccu.txt | 7 - Above text taken from NXP LPC1850 User Manual.
10 Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible:
14 Should be "nxp,lpc1850-ccu"
15 - reg:
18 - #clock-cells:
19 Shall have value <1>. The permitted clock-specifier values
21 - clocks:
23 from the CGU to the specific CCU. See mapping of base clocks
25 - clock-names:
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-flash.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
10 controller devices. Flash controller devices are typically used in
17 .. _flash-controls-use-cases:
24 ------------------------------------------
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
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