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/Documentation/devicetree/bindings/cache/
Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
17 "fsl,mpc8544-l2-cache-controller"
[all …]
/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,ddr.yaml7 title: Freescale DDR memory controller
15 pattern: "^memory-controller@[0-9a-f]+$"
21 - fsl,qoriq-memory-controller-v4.4
22 - fsl,qoriq-memory-controller-v4.5
23 - fsl,qoriq-memory-controller-v4.7
24 - fsl,qoriq-memory-controller-v5.0
25 - const: fsl,qoriq-memory-controller
27 - fsl,bsc9132-memory-controller
28 - fsl,mpc8536-memory-controller
29 - fsl,mpc8540-memory-controller
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
6 controller in some SoCs, e.g. Hisilicon SD5203.
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
27 /* dw_apb_ictl is used as secondary interrupt controller */
28 aic: interrupt-controller@3000 {
[all …]
Dmarvell,mpic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
33 interrupt controller.
35 interrupt-controller: true
40 msi-controller: true
45 - interrupt-controller
47 - msi-controller
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
Dfaraday,ftintc010.txt1 * Faraday Technologt FTINTC010 interrupt controller
3 This interrupt controller is a stock IP block from Faraday Technology found
9 "cortina,gemini-interrupt-controller" (deprecated)
10 - reg: The register bank for the interrupt controller.
11 - interrupt-controller: Identifies the node as an interrupt controller
13 Must be 2 as the controller can specify level or rising edge
16 interrupt-controller/interrupts.txt
20 interrupt-controller@48000000 {
23 interrupt-controller;
Dmarvell,odmi-controller.txt4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
32 compatible = "marvell,ap806-odmi-controller",
33 "marvell,odmi-controller";
34 interrupt-controller;
35 msi-controller;
Dmti,cpu-interrupt-controller.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
7 title: MIPS CPU Interrupt Controller
11 IRQs from a devicetree file and create a irq_domain for IRQ controller.
14 platforms internal interrupt controller cascade.
21 const: mti,cpu-interrupt-controller
29 interrupt-controller: true
37 - interrupt-controller
41 interrupt-controller {
42 compatible = "mti,cpu-interrupt-controller";
45 interrupt-controller;
Dmarvell,orion-intc.txt3 * Main interrupt controller
8 - interrupt-controller: identifies the node as an interrupt controller
18 intc: interrupt-controller {
20 interrupt-controller;
26 * Bridge interrupt controller
31 - interrupts: bridge interrupt of the main interrupt controller
32 - interrupt-controller: identifies the node as an interrupt controller
37 controller, defaults to 32 if not set
40 bridge_intc: interrupt-controller {
42 interrupt-controller;
Dloongson,cpu-interrupt-controller.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,cpu-interrupt-controller.yaml#
7 title: LoongArch CPU Interrupt Controller
14 const: loongson,cpu-interrupt-controller
19 interrupt-controller: true
26 - interrupt-controller
30 interrupt-controller {
31 compatible = "loongson,cpu-interrupt-controller";
33 interrupt-controller;
Dmarvell,armada-8k-pic.txt1 Marvell Armada 7K/8K PIC Interrupt controller
5 controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
6 typically connected to the GIC as the primary interrupt controller.
10 - interrupt-controller: identifies the node as an interrupt controller
12 controller. Should be 1
13 - reg: the register area for the PIC interrupt controller
14 - interrupts: the interrupt to the primary interrupt controller,
19 pic: interrupt-controller@3f0100 {
23 interrupt-controller;
Dmarvell,sei.txt1 Marvell SEI (System Error Interrupt) Controller
4 Marvell SEI (System Error Interrupt) controller is an interrupt
7 controller.
9 This interrupt controller can handle up to 64 SEIs, a set comes from the
22 - interrupt-controller: identifies the node as an interrupt controller
24 - msi-controller: identifies the node as an MSI controller for the CPs
29 sei: interrupt-controller@3f0200 {
34 interrupt-controller;
35 msi-controller;
/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt6 Every GPIO controller node must have #gpio-cells property defined,
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
29 - gpio-controller: Marks the port as GPIO controller.
32 - interrupt-controller: Empty boolean property which marks the GPIO
33 module as an IRQ controller.
36 this interrupt controller. The first cell
43 Example of gpio-controller nodes for a MPC8347 SoC:
[all …]
Dgpio-mxs.yaml7 title: Freescale MXS GPIO controller
13 The Freescale MXS GPIO controller is part of MXS PIN controller.
15 As the GPIO controller is embedded in the PIN controller and all the
16 GPIO ports share the same IO space with PIN controller, the GPIO node
49 interrupt-controller: true
57 gpio-controller: true
63 - interrupt-controller
66 - gpio-controller
90 gpio-controller;
92 interrupt-controller;
[all …]
Dgpio-thunderx.txt1 Cavium ThunderX/OCTEON-TX GPIO controller bindings
4 - reg: The controller bus address.
5 - gpio-controller: Marks the device node as a GPIO controller.
7 - First cell is the GPIO pin number relative to the controller.
12 - interrupt-controller: Marks the device node as an interrupt controller.
14 "interrupt-controller" is present.
15 - First cell is the GPIO pin number relative to the controller.
23 gpio-controller;
25 interrupt-controller;
Dgpio-altera.txt1 Altera GPIO controller bindings
6 - reg: Physical base address and length of the controller's registers.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
13 - The first cell is the GPIO offset number within the GPIO controller.
17 hardware is synthesized. This field is required if the Altera GPIO controller
20 controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
41 gpio-controller;
43 interrupt-controller;
Dgpio-xgene.txt1 APM X-Gene SoC GPIO controller bindings
3 This is a gpio controller that is part of the flash controller.
4 This gpio controller controls a total of 48 gpios.
7 - compatible: "apm,xgene-gpio" for X-Gene GPIO controller
8 - reg: Physical base address and size of the controller's registers
14 - gpio-controller: Marks the device node as a GPIO controller.
20 gpio-controller;
Dcdns,gpio.txt1 Cadence GPIO controller bindings
11 - gpio-controller: marks the device as a GPIO controller.
13 the GPIO controller.
16 - ngpios: integer number of gpio lines supported by this controller, up to 32.
18 - interrupt-controller: marks the device as an interrupt controller. When
24 <dt-bindings/interrupt-controller/irq.h>.
29 gpio0: gpio-controller@fd060000 {
38 gpio-controller;
41 interrupt-controller;
Dbrcm,xgs-iproc-gpio.yaml7 title: Broadcom XGS iProc GPIO controller
13 This controller is the Chip Common A GPIO present on a number of Broadcom
22 - description: the I/O address containing the GPIO controller registers.
25 gpio-controller: true
34 interrupt-controller: true
46 - gpio-controller
51 interrupt-controller: [ interrupts ]
55 #include <dt-bindings/interrupt-controller/irq.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
63 gpio-controller;
[all …]
/Documentation/devicetree/bindings/pci/
Dpci-msi.txt23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
66 msi: msi-controller@a {
68 compatible = "vendor,some-controller";
69 msi-controller;
[all …]
Daardvark-pci.txt1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
16 - msi-controller: indicates that the PCIe controller can itself
18 - msi-parent: pointer to the MSI controller to be used
26 In addition, the Device Tree describing an Aardvark PCIe controller
27 must include a sub-node that describes the legacy interrupt controller
28 built into the PCIe controller. This sub-node must have the following
[all …]
/Documentation/devicetree/bindings/mux/
Dmux-consumer.yaml7 title: Common multiplexer controller consumer
13 Mux controller consumers should specify a list of mux controllers that they
18 mux-ctrl-phandle : phandle to mux controller node
20 given mux controller (controller specific)
22 Mux controller properties should be named "mux-controls". The exact meaning of
23 each mux controller property must be documented in the device tree binding for
28 If it is required to provide the state that the mux controller needs to
34 the consumers want to control the mux controller. If the consumer needs
35 needs to set multiple states in a mux controller, then property
37 controller to a given state then property "mux-states" can be used.
[all …]
Dmux-controller.yaml4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
7 title: Common multiplexer controller provider
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
19 A mux controller provides a number of states to its consumers, and the state
24 Mux controller nodes
27 Mux controller nodes must specify the number of cells used for the
32 Optionally, mux controller nodes can also specify the state the mux should
34 idle-state is not present, the mux controller is typically left as is when
[all …]
/Documentation/devicetree/bindings/access-controllers/
Daccess-controllers.yaml18 or a group of hardware blocks. An access controller's domain is the set of
19 resources covered by the access controller.
22 controller provided by access-controllers property. In this case, the device
23 is a consumer and the access controller is the provider.
25 An access controller can be represented by any node in the device tree and
28 and a set of phandle arguments, specified by '#access-controller-cells'
29 property in the access controller node.
33 controller. The capabilities of each access controller are defined by the
34 binding of the access controller device.
42 "#access-controller-cells":
[all …]
/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
7 title: Hisilicon system controller
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
18 Hisilicon system controller, but some same registers located at different
19 offset. In addition, the HiP01 system controller has some specific control
22 The compatible names of each system controller are as follows:
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
[all …]
/Documentation/devicetree/bindings/clock/
Dmediatek,mt8195-clock.yaml7 title: MediaTek Functional Clock Controller for MT8195
66 scp_adsp: clock-controller@10720000 {
73 imp_iic_wrap_s: clock-controller@11d03000 {
80 imp_iic_wrap_w: clock-controller@11e05000 {
87 mfgcfg: clock-controller@13fbf000 {
94 wpesys: clock-controller@14e00000 {
101 wpesys_vpp0: clock-controller@14e02000 {
108 wpesys_vpp1: clock-controller@14e03000 {
115 imgsys: clock-controller@15000000 {
122 imgsys1_dip_top: clock-controller@15110000 {
[all …]

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