Searched full:core0 (Results 1 – 11 of 11) sorted by relevance
| /Documentation/devicetree/bindings/gpu/ |
| D | brcm,bcm-v3d.yaml | 27 - description: core0 register (required)
35 - const: core0
71 reg-names = "hub", "core0", "bridge", "gca";
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| D | arm,mali-bifrost.yaml | 184 - const: core0
209 - const: core0
227 - const: core0
243 - const: core0
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,sdm845-venus.yaml | 38 video-core0:
93 - video-core0
116 video-core0 {
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| D | qcom,sdm845-venus-v2.yaml | 63 video-core0:
91 - video-core0
123 video-core0 {
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| D | ti,cal.yaml | 36 - description: The RX Core0 (DPHY0) register region
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| D | mediatek,vcodec-subdev-decoder.yaml | 32 | (lat/lat soc/core0/core1) |
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 194 core0 {
214 core0 {
236 core0 {
255 core0 {
413 core0 {
428 core0 {
507 core0 {
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| D | cpu-capacity.txt | 74 core0 {
83 core0 {
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-r5f-rproc.yaml | 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
144 # The following properties are mandatory for R5F Core0 in both LockStep and Split
296 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2-kryo-cpu.yaml | 187 core0 {
197 core0 {
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| /Documentation/devicetree/bindings/mailbox/ |
| D | ti,omap-mailbox.yaml | 295 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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