Searched full:cores (Results 1 – 25 of 184) sorted by relevance
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| /Documentation/admin-guide/ |
| D | lockup-watchdogs.rst | 67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
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| /Documentation/devicetree/bindings/timer/ |
| D | snps,arc-timer.txt | 4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
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| /Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 13 For most flexcan IP cores the driver supports 2 RX modes:
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
28 cores come up in a mode where RTR reception is possible.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
48 some IP cores RTR frames cannot be received anymore.
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| D | xlnx,video.txt | 8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
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| D | baikal,bt1-axi.yaml | 15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,pru-consumer.yaml | 37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
50 should correspond to the PRU cores listed in the 'ti,prus' property. The
52 and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
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| D | mtk,scp.yaml | 88 The other cores are represented as child nodes of the boot core.
94 cores. The power of cache, SRAM and L1TCM power should be enabled
95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
98 The SCP cores do not use an MMU, but has a set of registers to
123 initializing sub cores of multi-core SCP.
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| D | ti,pru-rproc.yaml | 7 title: TI Programmable Realtime Unit (PRU) cores
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
20 PRU cores called RTUs with slightly different IP integration. The K3 SoCs
22 auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU
73 and the PRU/RTU cores. For the values of the interrupt cells please refer
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
77 cores in a test chip on the core tile. See ARM DDI 0498D.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
85 cores in a big.LITTLE configuration. It also features the MALI T624
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| /Documentation/locking/ |
| D | percpu-rw-semaphore.rst | 9 cores take the lock for reading, the cache line containing the semaphore
10 is bouncing between L1 caches of the cores, causing performance
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-bcma | 14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
89 That covers the general approach to binding xilinx IP cores into the
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| /Documentation/admin-guide/perf/ |
| D | arm_dsu_pmu.rst | 5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
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| D | dwc_pcie_pmu.rst | 2 Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)
5 DesignWare Cores (DWC) PCIe PMU
14 collection of statistics, Synopsys DesignWare Cores PCIe controller
46 DesignWare Cores (DWC) PCIe PMU Driver
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| /Documentation/arch/x86/ |
| D | topology.rst | 24 threads, cores, packages, etc.
36 - cores
41 Packages contain a number of cores plus shared resources, e.g. DRAM
56 The number of cores in a package.
69 and deduced from the APIC IDs of the cores in the package.
95 Cores chapter
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| /Documentation/devicetree/bindings/power/ |
| D | renesas,apmu.yaml | 40 Array of phandles pointing to CPU cores, which should match the order of
41 CPU cores used by the WUPCR and PSTR registers in the Advanced Power
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| /Documentation/admin-guide/device-mapper/ |
| D | unstriped.rst | 85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped on top of Intel NVMe device that has 2 cores
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.yaml | 10 RISC-V cores include Control Status Registers (CSRs) which are local to
19 cores. The timer interrupt comes from an architecturally mandated real-
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| D | snps,archs-intc.txt | 1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
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| D | openrisc,ompic.txt | 7 size is based on the number of cores the controller has been configured
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
51 processor cores, the memories node, an INTC node and an MDIO node represented
304 that is common to all the PRU cores. This should be represented as an
319 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
322 present on K3 SoCs have additional auxiliary PRU cores with slightly
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| /Documentation/devicetree/bindings/arc/ |
| D | axs103.txt | 5 HS38x cores.
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| /Documentation/devicetree/bindings/usb/ |
| D | iproc-udc.txt | 5 on Synopsys Designware Cores AHB Subsystem Device Controller
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