Searched +full:counter +full:- +full:2 (Results 1 – 25 of 243) sorted by relevance
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| /Documentation/devicetree/bindings/counter/ |
| D | interrupt-counter.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
22 const: interrupt-counter
31 - compatible
34 - required: [ interrupts-extended ]
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 1 What: /sys/bus/counter/devices/counterX/cascade_counts_enable
3 Contact: linux-iio@vger.kernel.org
5 Indicates the cascading of Counts on Counter X.
9 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select
11 Contact: linux-iio@vger.kernel.org
14 Counter X.
16 MTCLKA-MTCLKB:
20 MTCLKC-MTCLKD:
24 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
26 Contact: linux-iio@vger.kernel.org
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| D | sysfs-bus-iio-timer-stm32 | 8 - "reset"
11 - "enable"
12 The Counter Enable signal CNT_EN is used
14 - "update"
18 - "compare_pulse"
21 - "OC1REF"
23 - "OC2REF"
25 - "OC3REF"
27 - "OC4REF"
32 - "OC5REF"
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| /Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 7 counters is implemented. This is controlled by the CSV modes programmed in counter
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
13 interrupt is raised. If any other counter overflows, it continues counting, and
16 The "format" directory describes format of the config (event ID) and config1/2
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
33 un-supported, and value 1 for supported.
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| /Documentation/driver-api/ |
| D | generic-counter.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Generic Counter Interface
10 Counter devices are prevalent among a diverse spectrum of industries.
13 resolve the issue of duplicate code found among existing counter device
14 drivers by introducing a generic counter interface for consumption. The
15 Generic Counter interface enables drivers to support and expose a common
16 set of components and functionality present in counter devices.
21 Counter devices can vary greatly in design, but regardless of whether
23 counter devices consist of a core set of components. This core set of
24 components, shared by all counter devices, is what forms the essence of
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stm32-lptimer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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| D | st,stm32-timers.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
24 const: st,stm32-timers
32 clock-names:
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| /Documentation/w1/slaves/ |
| D | w1_ds2423.rst | 6 * Maxim DS2423 based counter devices.
17 -----------
21 available in DS2423 pages 12 - 15.
23 Result of each page is provided as an ASCII output where each counter
26 Each lines will contain the values of 42 bytes read from the counter and
30 a counter value expressed as an integer after c=
34 - 1 byte from ram page
35 - 4 bytes for the counter value
36 - 4 zero bytes
37 - 2 bytes for crc16 which was calculated from the data read since the previous crc bytes
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| /Documentation/arch/arm64/ |
| D | perf.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 :Date: 2019-03-06
16 ------------
24 --------------
39 ----------
46 For a non-VHE host this attribute will exclude EL2 as we consider the
55 ----------------------------
59 The KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE
60 kernel or non-VHE hypervisor).
65 exclusively rely on the PMU's hardware exception filtering - therefore we
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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| D | nxp,sysctr-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP System Counter Module(sys_ctr)
10 - Bai Ping <ping.bai@nxp.com>
13 The system counter(sys_ctr) is a programmable system counter
15 etc. it is intended for use in applications where the counter
22 - nxp,imx95-sysctr-timer
23 - nxp,sysctr-timer
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| D | fsl,ftm-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/fsl,ftm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
14 const: fsl,ftm-timer
24 contain an entry for each entry in clock-names.
28 clock-names:
30 - const: ftm-evt
31 - const: ftm-src
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| D | ti,da830-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kousik Sanagavarapu <five231003@gmail.com>
13 This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
14 can be configured as a general-purpose 64-bit timer, dual general-purpose
15 32-bit timers. When configured as dual 32-bit timers, each half can operate
18 The timer is a free running up-counter and can generate interrupts when the
19 counter reaches preset counter values.
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| D | nxp,tpm-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
15 management applications. The counter, compare and capture registers
17 power modes. TPM can support global counter bus where one TPM drives
18 the counter bus for the others, provided bit width is the same.
23 - const: fsl,imx7ulp-tpm
24 - items:
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| D | brcm,bcm2835-system-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The System Timer peripheral provides four 32-bit timer channels and a
15 single 64-bit free running counter. Each channel has an output compare
17 free running counter values, and generates an interrupt.
21 const: brcm,bcm2835-system-timer
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| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | counters.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
21 There are several counter groups based on where the counter is being counted. In
22 addition, each group of counters may have different counter types.
24 These counter groups are based on which component in a networking setup,
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
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| /Documentation/devicetree/bindings/watchdog/ |
| D | starfive,jh7100-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
17 output(WDOGINT) will rise when counter is 0. The counter will reload
18 the timeout value. And then, if counter decreases to 0 again and WDOGINT
25 - enum:
26 - starfive,jh7100-wdt
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| /Documentation/hwmon/ |
| D | sl28cpld.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
17 -----------
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
30 -------------
35 fan1_input Fan RPM. Assuming 2 pulses per revolution.
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| /Documentation/timers/ |
| D | timekeeping.rst | 10 If you grep through the kernel source you will find a number of architecture-
12 architecture-specific overrides of the sched_clock() function and some
17 on this timeline, providing facilities such as high-resolution timers.
23 -------------
30 Typically the clock source is a monotonic, atomic counter which will provide
31 n bits which count from 0 to (2^n)-1 and then wraps around to 0 and start over.
36 shall be as stable and correct as possible as compared to a real-world wall
41 the counter register is read in two phases on the bus lowest 16 bits first
42 and the higher 16 bits in a second bus cycle with the counter bits
44 values from the counter.
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| /Documentation/networking/ |
| D | snmp_counter.rst | 2 SNMP counter
10 these counters won't be changed by layer 2 packets (such as STP) or
17 .. _RFC1213 ipInReceives: https://tools.ietf.org/html/rfc1213#page-26
30 .. _RFC1213 ipInDelivers: https://tools.ietf.org/html/rfc1213#page-28
41 .. _RFC1213 ipOutRequests: https://tools.ietf.org/html/rfc1213#page-28
60 .. _Explicit Congestion Notification: https://tools.ietf.org/html/rfc3168#page-6
65 IpExtInNoECTPkts counts 2 or more.
73 .. _RFC1213 ipInHdrErrors: https://tools.ietf.org/html/rfc1213#page-27
78 scenarios: (1) The IP address is invalid. (2) The destination IP
81 .. _RFC1213 ipInAddrErrors: https://tools.ietf.org/html/rfc1213#page-27
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
13 2) Timing Devices
32 information relevant to KVM and hardware-based virtualization.
34 2. Timing Devices
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
48 counters. Channel 1 and 2 were not available for general use in the original
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
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| /Documentation/devicetree/bindings/rtc/ |
| D | loongson,rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Real-Time Clock
10 The Loongson family chips use an on-chip counter 0 (Time Of Year
11 counter) as the RTC.
14 - Binbin Zhou <zhoubinbin@loongson.cn>
17 - $ref: rtc.yaml#
22 - enum:
23 - loongson,ls1b-rtc
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| /Documentation/arch/powerpc/ |
| D | imc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 IMC (In-Memory Collection Counters)
17 IMC (In-Memory collection counters) is a hardware monitoring facility that
19 on-chip but off-core), Core level and Thread level.
22 (On-Chip Controller) complex. The microcode collects the counter data and moves
23 the nest IMC counter data to memory.
33 - Event name
34 - Event Offset
35 - Event description
39 - Event scale
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| /Documentation/devicetree/bindings/pwm/ |
| D | imx-tpm-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 The TPM counter and period counter are shared between multiple
19 - $ref: pwm.yaml#
22 "#pwm-cells":
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| /Documentation/devicetree/bindings/perf/ |
| D | arm,smmu-v3-pmcg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm SMMUv3 Performance Monitor Counter Group
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
20 pattern: "^pmu@[0-9a-f]*"
23 - items:
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