Searched full:counters (Results 1 – 25 of 186) sorted by relevance
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| /Documentation/arch/arm64/ |
| D | amu.rst | 22 counters intended for system management use. The AMU extension provides a
27 of four fixed and architecturally defined 64-bit event counters.
37 When in WFI or WFE these counters do not increment.
40 event counters. Future versions of the architecture may use this space to
41 implement additional architected event counters.
44 64-bit event counters.
46 On cold reset all counters reset to 0.
59 counters, only the presence of the extension.
66 - Enable the counters. If not enabled these will read as 0.
67 - Save/restore the counters before/after the CPU is being put/brought up
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| D | perf.rst | 85 On non-VHE hosts we enable/disable counters on the entry/exit of host/guest
87 enabling/disabling the counters and entering/exiting the guest. We are
88 able to eliminate counters counting host events on the boundaries of guest
101 abstraction layer over the hardware counters since the underlying
104 hardware counters' values directly.
115 In order to have access to the hardware counters, the global sysctl
156 counters. Chained events are not supported in conjunction with userspace counter
157 access. If a 32-bit counter is requested on hardware with 64-bit counters, then
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| /Documentation/translations/zh_CN/core-api/ |
| D | local_ops.rst | 93 static DEFINE_PER_CPU(local_t, counters) = LOCAL_INIT(0);
105 local_inc(&get_cpu_var(counters));
106 put_cpu_var(counters);
110 local_inc(this_cpu_ptr(&counters));
123 sum += local_read(&per_cpu(counters, cpu));
143 static DEFINE_PER_CPU(local_t, counters) = LOCAL_INIT(0);
152 local_inc(this_cpu_ptr(&counters));
157 * local_inc(&get_cpu_var(counters));
158 * put_cpu_var(counters);
166 /* Increment the counters */
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| /Documentation/core-api/ |
| D | local_ops.rst | 30 counters. They minimize the performance cost of standard atomic operations by
34 Having fast per CPU atomic counters is interesting in many cases: it does not
36 coherent counters in NMI handlers. It is especially useful for tracing purposes
37 and for various performance monitoring counters.
95 static DEFINE_PER_CPU(local_t, counters) = LOCAL_INIT(0);
107 local_inc(&get_cpu_var(counters));
108 put_cpu_var(counters);
113 local_inc(this_cpu_ptr(&counters));
117 Reading the counters
120 Those local counters can be read from foreign CPUs to sum the count. Note that
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| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | counters.rst | 5 Ethtool counters
22 addition, each group of counters may have different counter types.
53 | Uplink (no counters) |
58 | MPFS (no counters) |
68 Software counters populated by the driver stack.
71 An aggregation of software ring counters.
73 vPort counters
74 Traffic counters and drops due to steering or no buffers. May indicate issues
75 with NIC. These counters include Ethernet traffic counters (including Raw
76 Ethernet) and RDMA/RoCE traffic counters.
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| /Documentation/admin-guide/perf/ |
| D | alibaba_pmu.rst | 23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
30 - Group 1: PMU Bandwidth Counters. This group has 8 counters that are used
32 selected rank, or four ranks separately in the first 4 counters. The base
35 - Group 2: PMU Retry Counters. This group has 10 counters, that intend to
38 - Group 3: PMU Common Counters. This group has 16 counters, that are used
41 For now, the Driveway PMU driver only uses counters in group 0 and group 3.
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| D | thunderx2-pmu.rst | 13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
14 counters. Counters are independently programmable to different events and
15 can be started and stopped individually. None of the counters support an
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
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| D | imx-ddr.rst | 5 There are no performance counters inside the DRAM controller, so performance
7 counters is implemented. This is controlled by the CSV modes programmed in counter
12 “time” and when expired causes a lock on itself and the other counters and an
50 event at the same time as this filter is shared between counters.
70 read and write transactions concurrently with another set of data counters.
74 at the same time as the filter is shared between counters. This quirk is the
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| D | qcom_l3_pmu.rst | 17 The hardware implements 32bit event counters and has a flat 8bit event space
19 counters the driver supports virtual 64bit hardware counters by using hardware
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| /Documentation/admin-guide/device-mapper/ |
| D | statistics.rst | 14 The I/O statistics counters for each step-sized area of a region are
16 Documentation/admin-guide/iostats.rst). But two extra counters (12 and 13) are
19 histogram of latencies. All these counters may be accessed by sending
111 Clear all the counters except the in-flight i/o counters.
133 Print counters for each step-sized area of a region.
149 counters
151 The first 11 counters have the same meaning as
168 Additional counters:
174 Atomically print and then clear all the counters except the
175 in-flight i/o counters. Useful when the client consuming the
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-caps | 21 maximum number of counters which can be shown in the u64 counters
24 the perf tool to parse the logged counters in each branch.
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| D | sysfs-kernel-irq | 44 is a comma-separated list of counters; one per CPU in CPU id
45 order. NOTE: This file consistently shows counters for all
47 which only shows counters for online CPUs.
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| D | sysfs-bus-pci-devices-aer_stats | 5 statistical counters indicate the errors "as seen/reported by the device".
7 counters may increment at its link partner (e.g. root port) because the
9 problematic endpoint itself (which may report all counters as 0 as it never
100 device, so these counters include them and are thus cumulative of all the error
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| D | sysfs-driver-qat_ras | 29 Description: (WO) Write to resets all error counters of a device.
31 The following example reports how to reset the counters::
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| D | debugfs-driver-qat | 7 Reported firmware counters::
79 Reported counters::
93 random engine and disables the fetching of heartbeat counters.
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| /Documentation/arch/powerpc/ |
| D | imc.rst | 5 IMC (In-Memory Collection Counters)
17 IMC (In-Memory collection counters) is a hardware monitoring facility that
21 The Nest PMU counters are handled by a Nest IMC microcode which runs in the OCC
25 The Core and Thread IMC PMU counters are handled in the core. Core level PMU
26 counters give us the IMC counters' data per core and thread level PMU counters
27 give us the IMC counters' data per CPU thread.
51 The kernel discovers the IMC counters information in the device tree at the
52 `imc-counters` device node which has a compatible field
53 `ibm,opal-in-memory-counters`. From the device tree, the kernel parses the PMUs
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| /Documentation/devicetree/bindings/arc/ |
| D | pct.txt | 1 * ARC Performance Counters
5 are 100+ hardware conditions dynamically mapped to up to 32 counters
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| D | snps,archs-pct.yaml | 7 title: ARC HS Performance Counters
15 are 100+ hardware conditions dynamically mapped to up to 32 counters.
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| /Documentation/locking/ |
| D | seqlock.rst | 2 Sequence counters and sequential locks
8 Sequence counters are a reader-writer consistency mechanism with
39 Sequence counters (``seqcount_t``)
92 Sequence counters with associated locks (``seqcount_LOCKNAME_t``)
97 sequence counters associate the lock used for writer serialization at
110 The following sequence counters with associated locks are defined:
144 Latch sequence counters (``seqcount_latch_t``)
147 Latch sequence counters are a multiversion concurrency control mechanism
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| /Documentation/RCU/ |
| D | rcu.rst | 43 counters. These counters allow limited types of blocking within
45 counters, and permits general blocking within RCU read-side
47 by sampling these counters.
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| /Documentation/devicetree/bindings/timer/ |
| D | nvidia,tegra186-timer.yaml | 13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
24 The Tegra186 timer provides ten 29-bit timer counters.
27 The Tegra234 timer provides sixteen 29-bit timer counters.
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| /Documentation/ABI/stable/ |
| D | sysfs-class-infiniband | 85 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/symbol_error
86 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_errors
87 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_remote_physical_errors
88 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_switch_relay_errors
89 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/link_error_recovery
90 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_constraint_errors
91 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_contraint_errors
92 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/local_link_integrity_errors
93 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/excessive_buffer_overrun_errors
94 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_data
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| D | sysfs-fs-orangefs | 5 Counters and settings for various caches.
14 reset all the counters in
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| /Documentation/admin-guide/ |
| D | numastat.rst | 7 All units are pages. Hugepages have separate counters.
9 The numa_hit, numa_miss and numa_foreign counters reflect how well processes
16 counters based on CPU local node. local_node is similar to numa_hit and is
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| /Documentation/arch/x86/ |
| D | tlb.rst | 65 performance counters and 'perf stat', like this::
76 may have differently-named counters, but they should at least
79 counters for a given CPU.
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