Searched +full:cpg +full:- +full:mstp +full:- +full:clocks (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks10 - Geert Uytterhoeven <geert+renesas@glider.be>13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are16 This device tree binding describes a single 32 gate clocks group per node.17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle23 - enum:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas Clock Pulse Generator (CPG)10 - Geert Uytterhoeven <geert+renesas@glider.be>13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It16 The CPG may also provide a Clock Domain for SoC devices, in combination with17 the CPG Module Stop (MSTP) Clocks.22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6[all …]