Searched +full:cpu +full:- +full:1 (Results 1 – 25 of 1004) sorted by relevance
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| /Documentation/arch/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
54 - topology_num_cores_per_package()
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-capacity.txt | 2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
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| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
20 from simple wfi to power gating) according to OS PM policies. The CPU states
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| /Documentation/scheduler/ |
| D | sched-bwc.rst | 6 This document only discusses CPU bandwidth control for SCHED_NORMAL.
7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
10 specification of the maximum CPU bandwidth available to a group or hierarchy.
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
32 (U = \Sum u_i) <= 1
35 stable. After all, if U were > 1, then for every second of walltime,
64 there many cgroups or CPU is under utilized, the interference is
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| /Documentation/admin-guide/ |
| D | cputopology.rst | 2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
10 Architecture-neutral, drivers/base/topology.c, exports these attributes.
16 these macros in include/asm-XXX/topology.h::
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
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| D | kernel-per-CPU-kthreads.rst | 2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
8 them to a "housekeeping" CPU dedicated to such work.
13 - Documentation/core-api/irq/irq-affinity.rst: Binding interrupts to sets of CPUs.
15 - Documentation/admin-guide/cgroup-v1: Using cgroups to bind tasks to sets of CPUs.
17 - man taskset: Using the taskset command to bind tasks to sets
20 - man sched_setaffinity: Using the sched_setaffinity() system
23 - /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
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| /Documentation/translations/zh_CN/mm/ |
| D | mmu_notifier.rst | 28 - 上页表锁
29 - 清除页表项并通知 ([pmd/pte]p_huge_clear_flush_notify())
30 - 设置页表项以指向新页
37 两个地址addrA和addrB，这样|addrA - addrB| >= PAGE_SIZE，我们假设它们是COW的
42 [Time N] --------------------------------------------------------------------
43 CPU-thread-0 {尝试写到addrA}
44 CPU-thread-1 {尝试写到addrB}
45 CPU-thread-2 {}
46 CPU-thread-3 {}
47 DEV-thread-0 {读取addrA并填充设备TLB}
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| /Documentation/core-api/ |
| D | cpu_hotplug.rst | 2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
27 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
53 CPU maps
66 after a CPU is available for kernel scheduling and ready to receive
67 interrupts from devices. Its cleared when a CPU is brought down using
69 migrated to another target CPU.
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cpu-debug.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CoreSight CPU Debug Component
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
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| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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| /Documentation/translations/zh_CN/scheduler/ |
| D | sched-bwc.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/scheduler/sched-bwc.rst
19 SCHED_RT的情况在Documentation/scheduler/sched-rt-group.rst中有涉及。
29 它以需求为基础被转移到cpu-local“筒仓”，在每次更新中转移的数量是可调整的，被描述为“片“（时
33 --------
37 传统的（UP-EDF）带宽控制是这样的:
39 (U = \Sum u_i) <= 1
41 这既保证了每个最后期限的实现，也保证了系统的稳定。毕竟，如果U>1，那么每一秒钟的壁钟时间，我
61 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
64 ----
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| /Documentation/mm/ |
| D | mmu_notifier.rst | 8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
41 CPU-thread-2 {}
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
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| /Documentation/devicetree/bindings/csky/ |
| D | cpus.txt | 2 C-SKY CPU Bindings
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
13 cpus and cpu node bindings definition
16 - cpus node
18 Description: Container of cpu nodes
24 - #address-cells
27 Definition: must be set to 1
28 - #size-cells
33 - cpu node
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,saw2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 power-controller that transitions a piece of hardware (like a processor or
27 - enum:
28 - qcom,ipq4019-saw2-cpu
29 - qcom,ipq4019-saw2-l2
30 - qcom,ipq8064-saw2-cpu
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
20 * Alpine CPU resume registers
22 The CPU resume register are used to define required resume address after
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
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| /Documentation/translations/zh_CN/admin-guide/ |
| D | cputopology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/admin-guide/cputopology.rst
15 /sys/devices/system/cpu/cpuX/topology/。请阅读ABI文件：
16 Documentation/ABI/stable/sysfs-devices-system-cpu。
21 对于支持这个特性的体系结构，它必须在include/asm-XXX/topology.h中定义这些宏中的一部分::
23 #define topology_physical_package_id(cpu)
24 #define topology_die_id(cpu)
25 #define topology_cluster_id(cpu)
26 #define topology_core_id(cpu)
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| /Documentation/translations/zh_TW/admin-guide/ |
| D | cputopology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_TW.rst
4 :Original: Documentation/admin-guide/cputopology.rst
15 /sys/devices/system/cpu/cpuX/topology/。請閱讀ABI文件：
16 Documentation/ABI/stable/sysfs-devices-system-cpu。
21 對於支持這個特性的體系結構，它必須在include/asm-XXX/topology.h中定義這些宏中的一部分::
23 #define topology_physical_package_id(cpu)
24 #define topology_die_id(cpu)
25 #define topology_cluster_id(cpu)
26 #define topology_core_id(cpu)
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| /Documentation/devicetree/bindings/mips/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
15 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
16 defining properties for every CPU.
21 - brcm,bmips3300
22 - brcm,bmips4350
23 - brcm,bmips4380
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟件。
51 1、設置和初始化 RAM
57 1、設置和初始化 RAM
58 -----------------
69 ---------------
81 -------------
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
47 1、设置和初始化 RAM
53 1、设置和初始化 RAM
54 -----------------
65 ---------------
77 -------------
87 -------------
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| /Documentation/cpu-freq/ |
| D | cpufreq-stats.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 1. Introduction
16 3. Configuring cpufreq-stats
19 1. Introduction
22 cpufreq-stats is a driver that provides CPU frequency statistics for each CPU.
25 in /sysfs (<sysfs root>/devices/system/cpu/cpuX/cpufreq/stats/) for each CPU.
29 that may be running on your CPU. So, it will work with any cpufreq_driver.
37 - time_in_state
38 - total_trans
39 - trans_table
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