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/Documentation/translations/zh_CN/mm/
Dmmu_notifier.rst28 - 上页表锁
29 - 清除页表项并通知 ([pmd/pte]p_huge_clear_flush_notify())
30 - 设置页表项以指向新页
37 两个地址addrA和addrB，这样|addrA - addrB| >= PAGE_SIZE，我们假设它们是COW的
42 [Time N] --------------------------------------------------------------------
43 CPU-thread-0 {尝试写到addrA}
44 CPU-thread-1 {尝试写到addrB}
45 CPU-thread-2 {}
46 CPU-thread-3 {}
47 DEV-thread-0 {读取addrA并填充设备TLB}
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/Documentation/mm/
Dmmu_notifier.rst8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
10 process virtual address space). There is only 2 cases when you need to notify
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
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/Documentation/devicetree/bindings/cpu/
Dcpu-capacity.txt2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
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Dcpu-topology.txt2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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/Documentation/translations/zh_TW/arch/arm64/
Dbooting.txt1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟件。
52 2、設置設備樹數據
58 -----------------
68 2、設置設備樹數據
69 ---------------
73 設備樹數據塊（dtb）必須 8 字節對齊，且大小不能超過 2MB。由於設備樹
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/Documentation/translations/zh_CN/arch/arm64/
Dbooting.txt12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
48 2、设置设备树数据
54 -----------------
64 2、设置设备树数据
65 ---------------
69 设备树数据块（dtb）必须 8 字节对齐，且大小不能超过 2MB。由于设备树
70 数据块将在使能缓存的情况下以 2MB 粒度被映射，故其不能被置于必须以特定
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/Documentation/admin-guide/
Dkernel-per-CPU-kthreads.rst2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
8 them to a "housekeeping" CPU dedicated to such work.
13 - Documentation/core-api/irq/irq-affinity.rst: Binding interrupts to sets of CPUs.
15 - Documentation/admin-guide/cgroup-v1: Using cgroups to bind tasks to sets of CPUs.
17 - man taskset: Using the taskset command to bind tasks to sets
20 - man sched_setaffinity: Using the sched_setaffinity() system
23 - /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
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Dcputopology.rst2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
10 Architecture-neutral, drivers/base/topology.c, exports these attributes.
16 these macros in include/asm-XXX/topology.h::
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
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/Documentation/arch/x86/
Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
54 - topology_num_cores_per_package()
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/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
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/Documentation/devicetree/bindings/cpufreq/
Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
15 current CPU frequency and efuse values.
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
28 - qcom,apq8064
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Dnvidia,tegra20-cpufreq.txt5 - clocks: Must contain an entry for the CPU clock.
6 See ../clocks/clock-bindings.txt for details.
7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
10 For each opp entry in 'operating-points-v2' table:
11 - opp-supported-hw: Two bitfields indicating:
13 1. CPU process ID mask
14 2. SoC speedo ID mask
17 1. CPU process ID mask
18 2. CPU speedo ID mask
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Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
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/Documentation/scheduler/
Dsched-capacity.rst5 1. CPU Capacity
9 ----------------
13 different performance characteristics - on such platforms, not all CPUs can be
16 CPU capacity is a measure of the performance a CPU can reach, normalized against
17 the most performant CPU in the system. Heterogeneous systems are also called
18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.
20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems
23 - not all CPUs may have the same microarchitecture (µarch).
24 - with Dynamic Voltage and Frequency Scaling (DVFS), not all CPUs may be
28 performance-oriented than the LITTLE ones (more pipeline stages, bigger caches,
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Dsched-stats.rst16 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel
17 release). Some counters make more sense to be per-runqueue; other to be
18 per-domain. Note that domains (and their associated information) will only
22 statistics for each cpu listed, and there may well be more than one
38 Note that any such script will necessarily be version-specific, as the main
42 CPU statistics
43 --------------
44 cpu<N> 1 2 3 4 5 6 7 8 9
52 2) This field is a legacy array expiration count field used in the O(1)
60 6) # of times try_to_wake_up() was called to wake up the local cpu
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/Documentation/cpu-freq/
Dcpufreq-stats.rst1 .. SPDX-License-Identifier: GPL-2.0
15 2. Statistics Provided (with example)
16 3. Configuring cpufreq-stats
22 cpufreq-stats is a driver that provides CPU frequency statistics for each CPU.
25 in /sysfs (<sysfs root>/devices/system/cpu/cpuX/cpufreq/stats/) for each CPU.
29 that may be running on your CPU. So, it will work with any cpufreq_driver.
32 2. Statistics Provided (with example)
37 - time_in_state
38 - total_trans
39 - trans_table
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/Documentation/core-api/
Dworkqueue.rst32 worker thread per CPU and a single threaded (ST) wq had one worker
33 thread system-wide. A single MT wq needed to keep around the same
35 wq users over the years and with the number of CPU cores continuously
42 worker pool. An MT wq could provide only one execution context per CPU
60 * Use per-CPU unified worker pools shared by all wq to provide
85 worker-pools.
87 The cmwq design differentiates between the user-facing workqueues that
89 which manages worker-pools and processes the queued work items.
91 There are two worker-pools, one for normal work items and the other
92 for high priority ones, for each possible CPU and some extra
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/Documentation/devicetree/bindings/
Dnuma.txt6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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/Documentation/translations/ko_KR/
Dmemory-barriers.txt2 This is a version of Documentation/memory-barriers.txt translated into Korean.
15 Documentation/memory-barriers.txt
39 일부 이상한 점들은 공식적인 메모리 일관성 모델과 tools/memory-model/ 에 있는
51 (2) 사용 가능한 배리어들에 대해 어떻게 사용해야 하는지에 대한 안내를 제공하기
60 해당 배리어의 명시적 사용이 불필요해서 no-op 이 될수도 있음을 알아두시기
76 - 디바이스 오퍼레이션.
77 - 보장사항.
81 - 메모리 배리어의 종류.
82 - 메모리 배리어에 대해 가정해선 안될 것.
83 - 주소 데이터 의존성 배리어 (역사적).
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/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
20 * Alpine CPU resume registers
22 The CPU resume register are used to define required resume address after
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
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/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8998-bwmon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
17 - Measuring the bandwidth between CPUs and Last Level Cache Controller -
19 - Measuring the bandwidth between Last Level Cache Controller and memory
20 (DDR) - called LLCC BWMON.
25 - const: qcom,msm8998-bwmon # BWMON v4
26 - items:
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/Documentation/ABI/testing/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
5 A collection of both global and individual CPU attributes
7 Individual CPU attributes are contained in subdirectories
8 named by the kernel's logical CPU number, e.g.:
10 /sys/devices/system/cpu/cpuX/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
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/Documentation/translations/zh_CN/core-api/
Dworkqueue.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/core-api/workqueue.rst
109 每个与实际CPU绑定的worker-pool通过钩住调度器来实现并发管理。每当
139 参数 - ``@name`` , ``@flags`` 和 ``@max_active`` 。
148 ---------
202 --------------
234 0 w0 starts and burns CPU
236 15 w0 wakes up and burns CPU
238 20 w1 starts and burns CPU
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/Documentation/translations/zh_CN/admin-guide/
Dcputopology.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/admin-guide/cputopology.rst
15 /sys/devices/system/cpu/cpuX/topology/。请阅读ABI文件：
16 Documentation/ABI/stable/sysfs-devices-system-cpu。
21 对于支持这个特性的体系结构，它必须在include/asm-XXX/topology.h中定义这些宏中的一部分::
23 #define topology_physical_package_id(cpu)
24 #define topology_die_id(cpu)
25 #define topology_cluster_id(cpu)
26 #define topology_core_id(cpu)
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