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/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
13 source, should be 1 for intc
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
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Dqca,ath79-misc-intc.txt7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
23 interrupt-controller@18060010 {
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
27 interrupt-parent = <&cpuintc>;
30 interrupt-controller;
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Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
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Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
4 directly to one of the HW INT lines on each CPU.
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
13 peripheral IRQs to be routed to any CPU
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
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Drealtek,rtl-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 interrupt to be routed to one parent CPU (hardware) interrupt, or left
18 - Birger Koblitz <mail@birger-koblitz.de>
19 - Bert Vermeulen <bert@biot.com>
20 - John Crispin <john@phrozen.org>
25 - items:
26 - enum:
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Dcsky,apb-intc.txt2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
20 - compatible
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
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Dbrcm,bcm2836-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2836 per-CPU interrupt controller
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
16 peripheral (GPU) events, which chain to the BCM2835-style interrupt
20 - $ref: /schemas/interrupt-controller.yaml#
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Dbrcm,bcm7038-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
21 peripheral IRQs to be routed to any CPU
[all …]
Dabilis,tb10x-ictl.txt5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
18 are mapped one-to-one to parent interrupts.
21 -------
23 intc: interrupt-controller { /* Parent interrupt controller */
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Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
28 Additional required properties for brcm,bcm2836-armctrl-ic:
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/Documentation/devicetree/bindings/cpufreq/
Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
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/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
[all …]
/Documentation/devicetree/bindings/arm/ux500/
Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
18 backupram: (used for CPU spin tables and for storing data
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
29 see binding for timer/arm,twd-timer.yaml
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/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
14 to get the current CPU ID
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
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/Documentation/devicetree/bindings/timer/
Drealtek,otto-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/realtek,otto-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 as a per CPU clock event generator and an overall CPU clocksource.
14 - Chris Packham <chris.packham@alliedtelesis.co.nz>
18 pattern: "^timer@[0-9a-f]+$"
22 - enum:
23 - realtek,rtl9302-timer
24 - const: realtek,otto-timer
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Dcsky,gx6605s-timer.txt16 - compatible
19 Definition: must be "csky,gx6605s-timer"
20 - reg
23 Definition: <phyaddr size> in soc from cpu view
24 - clocks
28 - interrupt
34 ---------
37 compatible = "csky,gx6605s-timer";
41 interrupt-parent = <&intc>;
Dcsky,mptimer.txt2 C-SKY Multi-processors Timer
5 C-SKY multi-processors timer is designed for C-SKY SMP system and the
6 regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
8 - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
9 - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
10 - PTIM_CCVR "cr<3, 14>" Current counter value reg.
11 - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event.
21 - compatible
25 - clocks
29 - interrupts
[all …]
/Documentation/devicetree/bindings/pci/
Dqcom,pcie-sa8775p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sa8775p
25 reg-names:
27 - const: parf # Qualcomm specific registers
28 - const: dbi # DesignWare PCIe registers
[all …]
Dqcom,pcie-sc8180x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sc8180x
25 reg-names:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
[all …]
Dqcom,pcie-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - qcom,pcie-sa8540p
21 - qcom,pcie-sc8280xp
27 reg-names:
30 - const: parf # Qualcomm specific registers
[all …]
Dqcom,pcie-sm8550.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - const: qcom,pcie-sm8550
21 - items:
22 - enum:
23 - qcom,pcie-sm8650
[all …]
Dqcom,pcie-x1e80100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-x1e80100
25 reg-names:
27 - const: parf # Qualcomm specific registers
28 - const: dbi # DesignWare PCIe registers
[all …]
/Documentation/devicetree/bindings/csky/
Dpmu.txt2 C-SKY Performance Monitor Units
5 C-SKY Performance Monitor is designed for ck807/ck810/ck860 SMP soc and
6 it could count cpu's events for helping analysis performance issues.
16 - compatible
19 Definition: must be "csky,csky-pmu"
20 - interrupts
24 - count-width
30 ---------
31 #include <dt-bindings/interrupt-controller/irq.h>
33 pmu: performace-monitor {
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/Documentation/arch/x86/i386/
DIO-APIC.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
11 hardware interrupts to multiple CPUs, or to CPU groups. Without an
12 IO-APIC, interrupts from hardware will be delivered only to the
13 CPU which boots the operating system (usually CPU#0).
16 multiple IO-APICs. Multiple IO-APICs are used in high-end servers to
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
23 If your box boots fine with enabled IO-APIC IRQs, then your
[all …]
/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
20 from simple wfi to power gating) according to OS PM policies. The CPU states
[all …]

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