Searched +full:cpu +full:- +full:pcie (Results 1 – 25 of 66) sorted by relevance
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| /Documentation/admin-guide/perf/ |
| D | nvidia-pmu.rst | 9 * NVLink-C2C0
10 * NVLink-C2C1
12 * PCIE
15 ----------
19 PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
22 the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
29 -------
31 The SCF PMU monitors system level cache events, CPU traffic, and
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
37 see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>.
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| D | meson-ddr-pmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
26 + arm - from CPU
27 + vpu_read1 - from OSD + VPP read
28 + gpu - from 3D GPU
29 + pcie - from PCIe controller
30 + hdcp - from HDCP controller
31 + hevc_front - from HEVC codec front end
32 + usb3_0 - from USB3.0 controller
33 + hevc_back - from HEVC codec back end
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCIe Endpoint Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
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| D | qcom,pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 reg-names:
26 interrupt-names:
30 iommu-map:
38 clock-names:
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| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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| D | qcom,pcie-sm8550.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
20 - const: qcom,pcie-sm8550
21 - items:
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| D | qcom,pcie-sc8180x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
19 const: qcom,pcie-sc8180x
25 reg-names:
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| D | qcom,pcie-sc8280xp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
20 - qcom,pcie-sa8540p
21 - qcom,pcie-sc8280xp
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| D | qcom,pcie-x1e80100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
19 const: qcom,pcie-x1e80100
25 reg-names:
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| D | qcom,pcie-sa8775p.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
19 const: qcom,pcie-sa8775p
25 reg-names:
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| D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
16 MT7621 PCIe HOST Topology
18 .-------.
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| D | mvebu-pci.txt | 1 * Marvell EBU PCIe interfaces
5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
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| D | nvidia,tegra20-pcie.txt | 1 NVIDIA Tegra PCIe controller
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
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| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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| /Documentation/translations/zh_CN/mm/ |
| D | hmm.rst | 1 .. include:: ../disclaimer-zh_CN.rst
18 HMM 还为 SVM（共享虚拟内存）提供了可选的帮助程序，即允许设备透明地访问与 CPU 一致的程序
19 地址，这意味着 CPU 上的任何有效指针也是该设备的有效指针。这对于简化高级异构计算的使用变得
23 部分中，我揭示了许多平台固有的硬件限制。第三部分概述了 HMM 设计。第四部分解释了 CPU 页
64 内存访问；甚至缓存一致性通常是可选的。从 CPU 访问设备内存甚至更加有限。通常情况下，它
67 如果我们只考虑 PCIE 总线，那么设备可以访问主内存（通常通过 IOMMU）并与 CPU 缓存一
68 致。但是，它只允许设备对主存储器进行一组有限的原子操作。这在另一个方向上更糟：CPU
72 另一个严重的因素是带宽有限（约 32GBytes/s，PCIE 4.0 和 16 通道）。这比最快的 GPU
76 一些平台正在开发新的 I/O 总线或对 PCIE 的添加/修改以解决其中一些限制
77 （OpenCAPI、CCIX）。它们主要允许 CPU 和设备之间的双向缓存一致性，并允许架构支持的所
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| /Documentation/arch/x86/ |
| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 addresses to physical addresses. SVA is what PCIe calls Shared Virtual
17 PCIe Address Translation Services (ATS) along with Page Request Interface
18 (PRI) allow devices to function much the same way as the CPU handling
19 application page-faults. For more information please refer to the PCIe
23 required to support the PCIe features ATS and PRI. ATS allows devices
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
28 CPU page tables. The device must use ATS again in order the fetch the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
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| /Documentation/devicetree/bindings/mfd/ |
| D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
30 - al,alpine-sysfabric-servic
31 - allwinner,sun8i-a83t-system-controller
32 - allwinner,sun8i-h3-system-controller
33 - allwinner,sun8i-v3s-system-controller
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 14 -----------------------------------
31 16 cpu CPU
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| /Documentation/scsi/ |
| D | hptiop.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 -----------------------
74 0x40-0x1040 Inbound Queue
75 0x1040-0x2040 Outbound Queue
99 0x1020C PCIe Function 0 Interrupt Enable
100 0x10400 PCIe Function 0 to CPU Message A
101 0x10420 CPU to PCIe Function 0 Message A
102 0x10480 CPU to PCIe Function 0 Doorbell
103 0x10484 CPU to PCIe Function 0 Doorbell Enable
108 ----------------------------------------
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| /Documentation/trace/ |
| D | hisi-ptt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 HiSilicon PCIe Tune and Trace device
10 HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
12 to dynamically monitor and tune the PCIe link's events (tune),
15 PCIe link's performance.
17 On Kunpeng 930 SoC, the PCIe Root Complex is composed of several
18 PCIe cores. Each PCIe core includes several Root Ports and a PTT
20 tracing the links of the PCIe core.
23 +--------------Core 0-------+
25 | | [Root Port]---[Endpoint]
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| /Documentation/arch/arm/sti/ |
| D | stih407-overview.rst | 6 ------------
8 The STiH407 is the new generation of SoC for Multi-HD, AVC set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz dual core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
17 ---------------
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| D | stih418-overview.rst | 6 ------------
8 The STiH418 is the new generation of SoC for UHDp60 set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz quad core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
15 - HEVC L5.1 Main 10
16 - VP9
19 ---------------
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-370-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
20 mpp4 4 gpio, vdd(cpu-pd)
33 mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
35 mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
71 mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
78 pcie(clkreq1)
83 pcie(clkreq0), spi1(cs1)
89 mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
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| /Documentation/networking/ |
| D | multi-pf-netdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Multi-PF Netdev
11 - `Background`_
12 - `Overview`_
13 - `mlx5 implementation`_
14 - `Channels distribution`_
15 - `Observability`_
16 - `Steering`_
17 - `Mutually exclusive features`_
22 The Multi-PF NIC technology enables several CPUs within a multi-socket server to connect directly to
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| /Documentation/arch/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
54 correspondence between a PCIe RID (bus/dev/fn) with a PE number.
57 - For DMA we then provide an entire address space for each PE that can
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
75 from the CPU address space to the PCI address space. There is one M32
78 the CPU address space to the PCIe bus and must be naturally aligned
81 - The M32 window:
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