Searched +full:cpu +full:- +full:power +full:- +full:controller (Results 1 – 25 of 150) sorted by relevance
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
12 initialization as well as a 'resets' phandle to the correct PMB controller as
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
20 Optional properties for the primary CPU node:
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| /Documentation/firmware-guide/acpi/ |
| D | lpit.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Low Power Idle Table (LPIT)
7 To enumerate platform Low Power Idle states, Intel platforms are using
8 “Low Power Idle Table” (LPIT). More details about this table can be
12 Residencies for each low power state can be read via FFH
18 - CPU PKG C10 (Read via FFH interface)
19 - Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface)
24 /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
25 /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
28 by the CPU package in PKG C10
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
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| /Documentation/devicetree/bindings/power/ |
| D | qcom,kpss-acc-v2.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power manager, and reset control to a Krait CPU.
14 There is one ACC register region per CPU within the KPSS remapped region as
16 with the CPU accessing the region. ACC v2 is currently used as a
17 power-manager for enabling the cpu.
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| D | renesas,rcar-sysc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/renesas,rcar-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car and RZ/G System Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car (RZ/G) System Controller provides power management for the CPU
16 The power domain IDs for consumers are defined in header files::
17 include/dt-bindings/power/r8*-sysc.h
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,saw2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 The Qualcomm Subsystem Power Manager is used to control the peripheral logic
17 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
19 power-controller that transitions a piece of hardware (like a processor or
20 subsystem) into and out of low power modes via a direct connection to
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| D | qcom,msm8976-ramp-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,msm8976-ramp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Ramp Controller
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
13 The Ramp Controller is used to program the sequence ID for pulse
15 CPU cores on some Qualcomm SoCs.
20 - qcom,msm8976-ramp-controller
26 - compatible
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| /Documentation/devicetree/bindings/soc/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
20 from simple wfi to power gating) according to OS PM policies. The CPU states
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| /Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 booting process handling and offloading the power management, clock
16 management, and reset control tasks from the CPU. The binding document
19 CPU and BPMP.
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,kpss-acc-v1.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
14 There is one ACC register region per CPU within the KPSS remapped region as
16 with the CPU accessing the region. ACC v1 is currently used as a
17 clock-controller for enabling the cpu and handling the aux clocks.
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| /Documentation/devicetree/bindings/display/msm/ |
| D | mdss-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 - Rob Clark <robdclark@gmail.com>
16 sub-blocks like DPU display controller, DSI and DP interfaces etc.
25 pattern: "^display-subsystem@[0-9a-f]+$"
30 reg-names:
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| D | qcom,qcm2290-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Loic Poulain <loic.poulain@linaro.org>
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,qcm2290-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AXI clock
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | apple,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
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| /Documentation/admin-guide/thermal/ |
| D | intel_powerclamp.rst | 6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | cpuctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon CPU controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The clock registers and power registers of secondary cores are defined
14 in CPU controller, especially in HIX5HD2 SoC.
19 - const: hisilicon,cpuctrl
24 "#address-cells":
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
9 With Intel(R) SST, one server can be configured for power and performance for a
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
25 how these commands change the power and performance profile of the system under
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
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| /Documentation/devicetree/bindings/usb/ |
| D | twlxxxx-usb.txt | 4 - compatible : Should be "ti,twl6030-usb"
5 - interrupts : Two interrupt numbers to the cpu should be specified. First
7 the controller has to act as host and the second interrupt number is the
8 usb interrupt number that raises VBUS interrupts when the controller has to
10 - usb-supply : phandle to the regulator device tree node. It should be vusb
13 twl6030-usb {
14 compatible = "ti,twl6030-usb";
19 &twl6030-usb {
20 usb-supply = <&vusb>;
24 - compatible : Should be "ti,twl4030-usb"
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| /Documentation/devicetree/bindings/mfd/ |
| D | sprd,sc27xx-pmic.txt | 1 Spreadtrum SC27xx Power Management Integrated Circuit (PMIC)
5 mobile handset power management, audio codec, battery management and user
8 - DCDCs to support CPU, memory.
9 - LDOs to support both internal and external requirement.
10 - Battery management system, such as charger, fuel gauge.
11 - Audio codec.
12 - User interface function, such as indicator, flash LED and so on.
13 - IC level interface, such as power on/off control, RTC and typec and so on.
16 - compatible: Should be one of the following:
22 - reg: The address of the device chip select, should be 0.
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| /Documentation/i2c/busses/ |
| D | i2c-ali15x3.rst | 2 Kernel driver i2c-ali15x3
12 - Frodo Looijaard <frodol@dds.nl>,
13 - Philip Edelbrock <phil@netroedge.com>,
14 - Mark D. Studebaker <mdsxyz123@yahoo.com>
17 -----------------
20 Initialize the base address of the i2c controller
24 -----
33 modprobe i2c-ali15x3 force_addr=0xe800
36 by a power cycle. Cause unknown (see Issues below).
40 -----------
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,sm8250-venus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sm8250-venus
23 power-domains:
27 power-domain-names:
30 - const: venus
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| D | qcom,sc7280-venus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sc7280-venus
23 power-domains:
27 power-domain-names:
30 - const: venus
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| D | qcom,sdm660-venus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
11 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
18 - $ref: qcom,venus-common.yaml#
22 const: qcom,sdm660-venus
27 clock-names:
29 - const: core
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| /Documentation/devicetree/bindings/thermal/ |
| D | rcar-thermal.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
5 $id: http://devicetree.org/schemas/thermal/rcar-thermal.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Thermal
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
16 - items:
17 - enum:
18 - renesas,thermal-r8a73a4 # R-Mobile APE6
19 - renesas,thermal-r8a7779 # R-Car H1
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