Searched +full:cpu +full:- +full:read (Results 1 – 25 of 384) sorted by relevance
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| /Documentation/core-api/ |
| D | local_ops.rst | 29 Local atomic operations are meant to provide fast and highly reentrant per CPU
34 Having fast per CPU atomic counters is interesting in many cases: it does not
40 CPU which owns the data. Therefore, care must taken to make sure that only one
41 CPU writes to the ``local_t`` data. This is done by using per cpu data and
43 however permitted to read ``local_t`` data from any CPU: it will then appear to
44 be written out of order wrt other memory writes by the owner CPU.
54 ``asm-generic/local.h`` in your architecture's ``local.h`` is sufficient.
66 * Variables touched by local ops must be per cpu variables.
67 * *Only* the CPU owner of these variables must write to them.
68 * This CPU can use local ops from any context (process, irq, softirq, nmi, ...)
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| D | this_cpu_ops.rst | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
24 Read-modify-write operations are of particular interest. Frequently
28 RMW (Read Modify Write) instructions like inc/dec/cmpxchg without the
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
65 ------------------------------------
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| D | protection-keys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Memory Protection Keys provide a mechanism for enforcing page-based
22 Protections for each key are defined with a per-CPU user-accessible register
23 (PKRU). Each of these is a 32-bit register storing two bits (Access Disable
26 Being a CPU register, PKRU is inherently thread-local, potentially giving each
30 register. The feature is only available in 64-bit mode, even though there is
40 Protections for each key are defined with a per-CPU user-writable system
41 register (POR_EL0). This is a 64-bit register encoding read, write and execute
44 Being a CPU register, POR_EL0 is inherently thread-local, potentially giving
61 application writes to the architecture specific CPU register directly in order
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| /Documentation/firmware-guide/acpi/ |
| D | lpit.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 Residencies for each low power state can be read via FFH
18 - CPU PKG C10 (Read via FFH interface)
19 - Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface)
24 /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
25 /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
28 by the CPU package in PKG C10
32 This is the lowest possible system power state, achieved only when CPU is in
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| /Documentation/mm/ |
| D | mmu_notifier.rst | 8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
41 CPU-thread-2 {}
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| /Documentation/hwmon/ |
| D | smsc47m192.rst | 10 Addresses scanned: I2C 0x2c - 0x2d
23 - Hartmut Rick <linux@rick.claranet.de>
25 - Special thanks to Jean Delvare for careful checking
30 -----------
33 of the SMSC LPC47M192 and compatible Super-I/O chips.
36 as well as CPU voltage VID input.
42 Voltages and temperatures are measured by an 8-bit ADC, the resolution
52 bit 4 of the encoded CPU voltage. This means that you either get
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
64 ---------------
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| /Documentation/RCU/ |
| D | checklist.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 0. Is RCU being applied to a read-mostly situation? If the data
18 tool for the job. Yes, RCU does reduce read-side overhead by
19 increasing write-side overhead, which is exactly why normal uses
27 Yet another exception is where the low real-time latency of RCU's
28 read-side primitives is critically important.
33 counter-intuitive situation where rcu_read_lock() and
49 them -- even x86 allows later loads to be reordered to precede
54 relating to itself that other tasks can read, there by definition
59 2. Do the RCU read-side critical sections make proper use of
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| D | rcu.rst | 6 The basic idea behind RCU (read-copy update) is to split destructive
11 since dropped their references. For example, an RCU-protected deletion
17 --------------------------
19 - Why would anyone want to use RCU?
21 The advantage of RCU's two-part approach is that RCU readers need
26 in read-mostly situations. The fact that RCU readers need not
27 acquire locks can also greatly simplify deadlock-avoidance code.
29 - How can the updater tell when a grace period has completed
33 block, switch to user-mode execution, or enter the idle loop.
34 Therefore, as soon as a CPU is seen passing through any of these
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| D | NMI-RCU.rst | 7 Although RCU is usually used to protect read-mostly data structures,
8 it is possible to use RCU to provide dynamic non-maskable interrupt
10 how to do this, drawing loosely from Zwane Mwaikambo's NMI-timer
16 static int dummy_nmi_callback(struct pt_regs *regs, int cpu)
23 the NMI handler to take the default machine-specific action::
32 int cpu;
36 cpu = smp_processor_id();
37 ++nmi_count(cpu);
39 if (!rcu_dereference_sched(nmi_callback)(regs, cpu))
46 in the same way that a hardware irq would, then increments the per-CPU
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| /Documentation/translations/zh_CN/core-api/ |
| D | local_ops.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/local_ops.rst
51 UP之间没有不同的行为，在你的架构的 ``local.h`` 中包括 ``asm-generic/local.h``
76 以确保它在-rt内核上仍能正确工作。
122 for_each_online_cpu(cpu)
123 sum += local_read(&per_cpu(counters, cpu));
133 /* test-local.c
147 /* IPI called on each CPU. */
151 printk("Increment on cpu %d\n", smp_processor_id());
164 int cpu;
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-slab | 5 Christoph Lameter <cl@linux-foundation.org>
17 Christoph Lameter <cl@linux-foundation.org>
19 The aliases file is read-only and specifies how many caches
26 Christoph Lameter <cl@linux-foundation.org>
28 The align file is read-only and specifies the cache's object
35 Christoph Lameter <cl@linux-foundation.org>
37 The alloc_calls file is read-only and lists the kernel code
46 Christoph Lameter <cl@linux-foundation.org>
57 Christoph Lameter <cl@linux-foundation.org>
59 The alloc_from_partial file shows how many times a cpu slab has
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| D | sysfs-driver-intel_sdsi | 8 on a CPU. X represents the socket instance (though not the
38 is available at http://github.com/intel/intel-sdsi
46 a CPU and monitor status information. The layout of this file
49 http://github.com/intel/intel-sdsi
57 the On Demand NVRAM for the CPU. The AKC is used to authenticate
66 On Demand NVRAM for the CPU. CAPs are used to activate a given
67 CPU feature. A CAP is validated by On Demand hardware using a
69 the CPU configuration is updated. A cold reboot is required to
77 (RO) Used to read back the current meter certificate for the CPU
87 (RO) Used to read back the current state certificate for the CPU
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| D | sysfs-platform-power-on-reason | 6 be read (the list can be extended):
7 "regular power-up", "RTC wakeup", "watchdog timeout",
8 "software reset", "reset button action", "CPU clock failure",
9 "crystal oscillator failure", "brown-out reset",
12 The file is read only.
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| /Documentation/ |
| D | memory-barriers.txt | 19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
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| /Documentation/RCU/Design/Requirements/ |
| D | Requirements.rst | 16 ------------
18 Read-copy update (RCU) is a synchronization mechanism that is often used
19 as a replacement for reader-writer locking. RCU is unusual in that
20 updaters do not block readers, which means that RCU's read-side
28 thought of as an informal, high-level specification for RCU. It is
40 #. `Fundamental Non-Requirements`_
42 #. `Quality-of-Implementation Requirements`_
44 #. `Software-Engineering Requirements`_
53 ------------------------
58 #. `Grace-Period Guarantee`_
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| /Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 management, and reset control tasks from the CPU. The binding document
19 CPU and BPMP.
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
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| /Documentation/arch/powerpc/ |
| D | dscr.rst | 21 dscr_default /* per-CPU DSCR default value */
29 Scheduler will write the per-CPU DSCR default which is stored in the
30 CPU's PACA value into the register if the thread has dscr_inherit value
35 the per-CPU default PACA based DSCR value.
42 - Global DSCR default: /sys/devices/system/cpu/dscr_default
43 - CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
45 Changing the global DSCR default in the sysfs will change all the CPU
48 value into every CPU's DSCR register right away and updates the current
51 Changing the CPU specific DSCR default value in the sysfs does exactly
53 stuff for that particular CPU instead for all the CPUs on the system.
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| /Documentation/locking/ |
| D | spinlocks.rst | 20 there is only one thread-of-control within the region(s) protected by that
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
46 to do locking across CPU's, which implies that EVERYTHING that
50 ----
52 Lesson 2: reader-writer spinlocks.
56 to mostly read from the shared variables, the reader-writer locks
61 NOTE! reader-writer locks require more atomic memory operations than
76 .. read and write exclusive access to the info ...
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| D | locktorture.rst | 30 Locktorture-specific
31 --------------------
49 - "lock_busted":
52 - "spin_lock":
55 - "spin_lock_irq":
58 - "rw_lock":
59 read/write lock() and unlock() rwlock pairs.
61 - "rw_lock_irq":
62 read/write lock_irq() and unlock_irq()
65 - "mutex_lock":
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| /Documentation/scheduler/ |
| D | sched-domains.rst | 5 Each CPU has a "base" scheduling domain (struct sched_domain). The domain
6 hierarchy is built from these base domains via the ->parent pointer. ->parent
7 MUST be NULL terminated, and domain structures should be per-CPU as they are
10 Each scheduling domain spans a number of CPUs (stored in the ->span field).
12 be relaxed if the need arises), and a base domain for CPU i MUST span at least
13 i. The top domain for each CPU will generally span all CPUs in the system
19 Each scheduling domain must have one or more CPU groups (struct sched_group)
20 which are organised as a circular one way linked list from the ->groups
22 domain's span. The group pointed to by the ->groups pointer MUST contain the CPU
24 read only data after they have been set up. The intersection of cpumasks from
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| /Documentation/filesystems/ |
| D | relay.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 to userspace via user-defined 'relay channels'.
11 A 'relay channel' is a kernel->user data relay mechanism implemented
12 as a set of per-cpu kernel buffers ('channel buffers'), each
15 functions; these automatically log into the current cpu's channel
16 buffer. User space applications mmap() or read() from the relay files
25 filtering - this also is left to the kernel client. The purpose is to
30 functions in the relay interface code - please see that for details.
35 Each relay channel has one buffer per CPU, each buffer has one or more
36 sub-buffers. Messages are written to the first sub-buffer until it is
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| /Documentation/driver-api/ |
| D | device-io.rst | 10 Bus-Independent Device Accesses
27 ----------------------------
30 part of the CPU's address space is interpreted not as accesses to
49 --------------------
52 memory-mapped registers on the device. Linux provides interfaces to read
53 and write 8-bit, 16-bit, 32-bit and 64-bit quantities. Due to a
55 Both read and write accesses are supported; there is no prefetch support
68 The read and write functions are defined to be ordered. That is the
77 driver author must issue a read from the same device to ensure that
80 cases, the read used to flush the device may be expected to fail (if the
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| D | io_ordering.rst | 2 Ordering I/O writes to memory-mapped addresses
5 On some platforms, so-called memory-mapped I/O is weakly ordered. On such
7 memory-mapped addresses on their device arrive in the order intended. This is
18 CPU A: spin_lock_irqsave(&dev_lock, flags)
19 CPU A: val = readl(my_status);
20 CPU A: ...
21 CPU A: writel(newval, ring_ptr);
22 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
24 CPU B: spin_lock_irqsave(&dev_lock, flags)
25 CPU B: val = readl(my_status);
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| /Documentation/admin-guide/acpi/ |
| D | cppc_sysfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 to request performance levels and to measure per-cpu delivered performance.
23 /sys/devices/system/cpu/cpuX/acpi_cppc/
25 for each cpu X::
27 $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/
28 /sys/devices/system/cpu/cpu0/acpi_cppc/:
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
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| /Documentation/ABI/obsolete/ |
| D | sysfs-cpuidle | 1 What: /sys/devices/system/cpu/cpuidle/current_governor_ro
3 Contact: linux-pm@vger.kernel.org
5 current_governor_ro shows current using cpuidle governor, but read only.
7 both current_governor and current_governor_ro co-exist under
8 /sys/devices/system/cpu/cpuidle/ file, it's duplicate so make
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