| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
22 "syscon"
[all …]
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| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
20 Optional properties for the primary CPU node:
21 - enable-method: should be "brcm,bcm63138"
[all …]
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| /Documentation/devicetree/bindings/soc/microchip/ |
| D | microchip,sparx5-cpu-syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,sparx5-cpu-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 CPU Syscon
10 - Lars Povlsen <lars.povlsen@microchip.com>
15 - const: microchip,sparx5-cpu-syscon
16 - const: syscon
17 - const: simple-mfd
22 mux-controller:
[all …]
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| /Documentation/devicetree/bindings/reset/ |
| D | microchip,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
25 - microchip,lan966x-switch-reset
29 - description: global control block registers
[all …]
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| /Documentation/devicetree/bindings/mfd/ |
| D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
14 a reference to the syscon node (e.g. by phandle, node path, or
20 - Lee Jones <lee@kernel.org>
24 # syscon fallback.
30 - al,alpine-sysfabric-servic
[all …]
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| /Documentation/devicetree/bindings/arm/ |
| D | syna.txt | 3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
32 * Marvell Berlin CPU control bindings
34 CPU control register allows various operations on CPUs, like resetting them
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
[all …]
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| D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
24 pluggable CPU modules, see ARM DUI 0303E.
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
[all …]
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| /Documentation/devicetree/bindings/opp/ |
| D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI CPU OPP (Operating Performance Points)
11 families, the CPU frequencies subset and the voltage value of each
18 This document extends the operating-points-v2 binding by providing
22 - Dhruva Gole <d-gole@ti.com>
25 - $ref: opp-v2-base.yaml#
29 const: operating-points-v2-ti-cpu
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | armada-37xx-wdt.txt | 1 * Armada 37xx CPU Watchdog Timer Controller
4 - compatible : must be "marvell,armada-3700-wdt"
5 - reg : base physical address of the controller and length of memory mapped
7 - clocks : the clock feeding the watchdog timer. See clock-bindings.txt
8 - marvell,system-controller : reference to syscon node for the CPU Miscellaneous
13 cpu_misc: system-controller@d000 {
14 compatible = "marvell,armada-3700-cpu-misc", "syscon";
19 compatible = "marvell,armada-3700-wdt";
21 marvell,system-controller = <&cpu_misc>;
|
| D | samsung-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
20 - enum:
21 - google,gs101-wdt # for Google gs101
22 - samsung,s3c2410-wdt # for S3C2410
23 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
24 - samsung,exynos5250-wdt # for Exynos5250
[all …]
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| /Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 7 - compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
12 o CPU chip regs:
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
23 syscon@71070000 {
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
35 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
36 - reg : Should contain registers location and length
39 syscon@10d0000 {
40 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
|
| /Documentation/devicetree/bindings/arm/marvell/ |
| D | ap80x-system-controller.txt | 6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
33 const: hisilicon,hi6220-sysctrl
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | mediatek,mt7621-sysc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The MT7621 has a PLL controller from where the cpu clock is provided
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
34 - const: syscon
[all …]
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| D | mediatek,mtmips-sysc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
18 These SoCs have an XTAL from where the cpu clock is
24 - enum:
25 - ralink,mt7620-sysc
26 - ralink,mt7628-sysc
27 - ralink,mt7688-sysc
[all …]
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| D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
[all …]
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
20 * Alpine CPU resume registers
22 The CPU resume register are used to define required resume address after
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
[all …]
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| /Documentation/devicetree/bindings/regmap/ |
| D | regmap.txt | 5 little-endian,
6 big-endian,
7 native-endian: See common-properties.txt for a definition
10 Regmap defaults to little-endian register access on MMIO based
11 devices, this is by far the most common setting. On CPU
12 architectures that typically run big-endian operating systems
13 (e.g. PowerPC), registers can be defined as big-endian and must
16 On SoCs that can be operated in both big-endian and little-endian
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
19 chips), "native-endian" is used to allow using the same device tree
[all …]
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| /Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
18 another: from CPU to SoC peripherals and between some SoC peripherals
23 accessible by means of the Baikal-T1 System Controller.
[all …]
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| /Documentation/devicetree/bindings/thermal/ |
| D | amlogic,thermal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guillaume La Roque <glaroque@baylibre.com>
14 $ref: thermal-sensor.yaml#
19 - items:
20 - enum:
21 - amlogic,g12a-cpu-thermal
22 - amlogic,g12a-ddr-thermal
23 - const: amlogic,g12a-thermal
[all …]
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| /Documentation/devicetree/bindings/arm/rockchip/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
15 This includes the power to the CPU cores.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
24 - rockchip,rk3128-pmu
25 - rockchip,rk3288-pmu
[all …]
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| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
6 L3C - L3 cache controller
7 IOB - IO bridge
8 MCB - Memory controller bridge
9 MC - Memory controller
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
16 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
17 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
[all …]
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt7622-wed.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
21 - enum:
22 - mediatek,mt7622-wed
23 - mediatek,mt7981-wed
24 - mediatek,mt7986-wed
[all …]
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | fsl,imx-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Co-Processor
10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
13 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx6sx-cm4
19 - fsl,imx7d-cm4
20 - fsl,imx7ulp-cm4
[all …]
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