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/Documentation/arch/loongarch/
Dirq-chip-model.rst8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
28 | IPI | --> | CPUINTC | <-- | Timer |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
62 to CPUINTC directly::
65 | IPI | --> | CPUINTC | <-- | Timer |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
93 to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts
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/Documentation/devicetree/bindings/interrupt-controller/
Dgoogle,goldfish-pic.txt14 cpuintc {
28 interrupt-parent = <&cpuintc>;
Dqca,ath79-misc-intc.txt27 interrupt-parent = <&cpuintc>;
40 interrupt-parent = <&cpuintc>;
Didt,32434-pic.yaml48 interrupt-parent = <&cpuintc>;
Dralink,rt2880-intc.yaml51 interrupt-parent = <&cpuintc>;
Dloongson,eiointc.yaml55 interrupt-parent = <&cpuintc>;
Dmscc,ocelot-icpu-intr.yaml61 interrupt-parent = <&cpuintc>;
Dingenic,intc.yaml64 interrupt-parent = <&cpuintc>;
Drealtek,rtl-intc.yaml103 interrupt-parent = <&cpuintc>;
Dloongson,liointc.yaml114 interrupt-parent = <&cpuintc>;
/Documentation/translations/zh_TW/arch/loongarch/
Dirq-chip-model.rst31 | IPI | --> | CPUINTC | <-- | Timer |
67 | IPI | --> | CPUINTC | <-- | Timer |
93 CPUINTC::
151 - CPUINTC：即《龍芯架構參考手冊卷一》第7.4節所描述的CSR.ECFG/CSR.ESTAT寄存器及其
/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst31 | IPI | --> | CPUINTC | <-- | Timer |
67 | IPI | --> | CPUINTC | <-- | Timer |
99 | IPI | --> | CPUINTC | <-- | Timer |
125 CPUINTC::
183 - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
/Documentation/devicetree/bindings/timer/
Dralink,cevt-systick.yaml35 interrupt-parent = <&cpuintc>;
Dingenic,sysost.yaml60 interrupt-parent = <&cpuintc>;
/Documentation/devicetree/bindings/gpio/
Didt,32434-gpio.yaml60 interrupt-parent = <&cpuintc>;
/Documentation/devicetree/bindings/remoteproc/
Dingenic,vpu.yaml75 interrupt-parent = <&cpuintc>;
/Documentation/devicetree/bindings/pci/
Dralink,rt3883-pci.txt117 interrupt-parent = <&cpuintc>;
/Documentation/devicetree/bindings/net/wireless/
Dmediatek,mt76.yaml288 interrupt-parent = <&cpuintc>;