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/Documentation/devicetree/bindings/crypto/
Dqcom,inline-crypto-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
10 - Bjorn Andersson <andersson@kernel.org>
15 - enum:
16 - qcom,sa8775p-inline-crypto-engine
17 - qcom,sc7180-inline-crypto-engine
18 - qcom,sc7280-inline-crypto-engine
[all …]
Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
16 it is defined as a subnode of the NPE, if crypto support is
21 const: intel,ixp4xx-crypto
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Dmarvell-cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 "marvell,armada-370-crypto"
9 "marvell,armada-xp-crypto"
10 "marvell,armada-375-crypto"
11 "marvell,armada-38x-crypto"
12 - reg: base physical address of the engine and length of memory mapped
14 but this representation is deprecated and marvell,crypto-srams should
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Daspeed,ast2500-hace.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
10 - Neal Liu <neal_liu@aspeedtech.com>
13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
15 divided into two independently engines - Hash Engine and Crypto Engine.
20 - aspeed,ast2500-hace
21 - aspeed,ast2600-hace
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Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
4 - compatible : Should be one of the following strings:
5 "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
6 "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
12 crypto@f4264000 {
13 compatible = "axis,artpec6-crypto";
Dmv_cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 - reg: base physical address of the engine and length of memory mapped
10 but this representation is deprecated and marvell,crypto-srams should
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
13 is deprecated and marvell,crypto-srams should be used instead
14 - interrupts: interrupt number
15 - clocks: reference to the crypto engines clocks. This property is only
[all …]
Dqcom-qce.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm crypto engine driver
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
13 This document defines the binding for the QCE crypto
19 - const: qcom,crypto-v5.1
23 - const: qcom,crypto-v5.4
27 - items:
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Dallwinner,sun4i-a10-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun4i-a10-crypto
17 - items:
18 - const: allwinner,sun5i-a13-crypto
19 - const: allwinner,sun4i-a10-crypto
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Damlogic,gxl-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Corentin Labbe <clabbe@baylibre.com>
15 - const: amlogic,gxl-crypto
22 - description: Interrupt for flow 0
23 - description: Interrupt for flow 1
28 clock-names:
32 - compatible
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Daspeed,ast2600-acry.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neal Liu <neal_liu@aspeedtech.com>
15 divided into two independent engines - ECC Engine and RSA Engine.
20 - aspeed,ast2600-acry
24 - description: acry base address & size
25 - description: acry sram base address & size
34 - compatible
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Dnvidia,tegra234-se-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for AES algorithms
10 The Tegra Security Engine accelerates the following AES encryption/decryption
11 algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
12 AES-CMAC
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-aes
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Dnvidia,tegra234-se-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Security Engine for HASH algorithms
10 The Tegra Security HASH Engine accelerates the following HASH functions -
11 SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-hash
30 dma-coherent: true
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Dallwinner,sun8i-ce.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Crypto Engine driver
10 - Corentin Labbe <clabbe.montjoie@gmail.com>
15 - allwinner,sun8i-h3-crypto
16 - allwinner,sun8i-r40-crypto
17 - allwinner,sun20i-d1-crypto
18 - allwinner,sun50i-a64-crypto
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Dintel,keembay-ocs-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
13 The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
14 hardware-accelerated AES/SM4 encryption/decryption.
18 const: intel,keembay-ocs-aes
30 - compatible
31 - reg
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Darm,cryptocell.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/arm,cryptocell.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm TrustZone CryptoCell cryptographic engine
10 - Gilad Ben-Yossef <gilad@benyossef.com>
15 - arm,cryptocell-713-ree
16 - arm,cryptocell-703-ree
17 - arm,cryptocell-712-ree
18 - arm,cryptocell-710-ree
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Dinside-secure,safexcel.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/crypto/inside-secure,safexcel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Inside Secure SafeXcel cryptographic engine
10 - Antoine Tenart <atenart@kernel.org>
15 - const: inside-secure,safexcel-eip197b
16 - const: inside-secure,safexcel-eip197d
17 - const: inside-secure,safexcel-eip97ies
18 - const: inside-secure,safexcel-eip197
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/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
[all …]
/Documentation/crypto/
Dcrypto_engine.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Crypto Engine
7 --------
8 The crypto engine (CE) API is a crypto queue manager.
11 -----------
18 struct crypto_engine engine;
22 The crypto engine only manages asynchronous requests in the form of
25 using container_of. In addition, the engine knows nothing about your
26 structure "``struct your_tfm_ctx``". The engine assumes (requires) the placement
30 -------------------
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Dasync-tx-api.rst1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
34 the details of different hardware offload engine implementations. Code
43 xor-parity-calculations of the md-raid5 driver using the offload engines
51 operation will be offloaded when an engine is available and carried out
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
64 -----------------------------
72 ------------------------
92 -------------------------
94 The return value is non-NULL and points to a 'descriptor' when the operation
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/Documentation/arch/powerpc/
Dvas-api.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
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/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt12 -----------------------------------
22 23 crypto CESA (crypto engine)
29 -----------------------------------
56 -----------------------------------
83 -----------------------------------
97 -----------------------------------
116 23 crypto CESA engine
124 -----------------------------------
134 -----------------------------------
147 15 crypto CESA engine
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/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
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/Documentation/devicetree/bindings/mailbox/
Dbrcm,iproc-flexrm-mbox.txt6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
15 The FlexRM engine will send MSIs (instead of wired
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
35 --------------------
36 - dma-coherent: Present if DMA operations made by the FlexRM engine (such
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/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
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/Documentation/driver-api/crypto/iaa/
Diaa-crypto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IAA Compression Accelerator Crypto Driver
9 The IAA crypto driver supports compression/decompression compatible
18 higher-level compression devices such as zswap.
25 represented by selecting the 'deflate-iaa' crypto compression
28 # echo deflate-iaa > /sys/module/zswap/parameters/compressor
37 specified by RFC 1951 and is given the crypto algorithm name
38 'deflate-iaa'. (Because the IAA hardware has a 4k history-window
49 The IAA crypto driver is available via menuconfig using the following
52 Cryptographic API -> Hardware crypto devices -> Support for Intel(R) IAA Compression Accelerator
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