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/Documentation/devicetree/bindings/gpio/
Dspear_spics.txt1 === ST Microelectronics SPEAr SPI CS Driver ===
13 the control of this interface as gpio.
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
[all …]
/Documentation/devicetree/bindings/spi/
Dbrcm,bcm2835-aux-spi.txt8 - compatible: Should be "brcm,bcm2835-aux-spi".
9 - reg: Should contain register location and length for the spi block
10 - interrupts: Should contain shared interrupt of the aux block
11 - clocks: The clock feeding the SPI controller - needs to
15 - cs-gpios: the cs-gpios (native cs is NOT supported)
16 see also spi-bus.txt
21 compatible = "brcm,bcm2835-aux-spi";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
[all …]
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
[all …]
Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
Dspi-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
14 dedicated GPIO lines.
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
[all …]
Dsamsung,spi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - enum:
20 - google,gs101-spi
21 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
22 - samsung,s3c6410-spi
23 - samsung,s5pv210-spi # for S5PV210 and S5PC110
24 - samsung,exynos4210-spi
[all …]
Dfsl-spi.txt4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
24 the cs-gpios property is not present.
28 cell-index = <0>;
[all …]
Dspi-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 MOSI /--------------------------------+--------+--------+--------\
17 MISO |/------------------------------+|-------+|-------+|-------\|
18 SCL ||/----------------------------+||------+||------+||------\||
20 +------------+ ||| ||| ||| |||
21 | SoC ||| | +-+++-+ +-+++-+ +-+++-+ +-+++-+
23 | +--+++-+ | CS-X +------+\ +--+--+ +--+--+ +--+--+ +--+--+
[all …]
Dnuvoton,npcm-pspi.txt6 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
7 "nuvoton,npcm845-pspi" for Arbel NPCM8XX.
8 - #address-cells : should be 1. see spi-bus.txt
9 - #size-cells : should be 0. see spi-bus.txt
10 - specifies physical base address and size of the register.
11 - interrupts : contain PSPI interrupt.
12 - clocks : phandle of PSPI reference clock.
13 - clock-names: Should be "clk_apb5".
14 - pinctrl-names : a pinctrl state named "default" must be defined.
15 - pinctrl-0 : phandle referencing pin configuration of the device.
[all …]
Dmicrochip,spi-pic32.txt4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
[all …]
Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
[all …]
/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 pattern: "^nand-controller(@.*)?"
23 "#address-cells":
26 "#size-cells":
31 cs-gpios:
[all …]
Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
31 mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
[all …]
Dqcom,sc7180-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,sc7180-pinctrl
23 reg-names:
25 - const: west
26 - const: north
[all …]
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
[all …]
/Documentation/iio/
Dad4000.rst1 .. SPDX-License-Identifier: GPL-2.0-only
30 ------------------
35 CS mode, 3-wire turbo mode
38 Datasheet "3-wire" mode is what most resembles standard SPI connection which,
39 for these devices, comprises of connecting the controller CS line to device CNV
41 "CS Mode, 3-Wire Turbo Mode" connection in datasheets.
42 NOTE: The datasheet definition of 3-wire mode for the AD4000 series is NOT the
43 same of standard spi-3wire mode.
47 Omit the ``adi,sdi-pin`` property in device tree to select this mode.
51 +-------------+
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7944.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of pin-compatible single channel differential analog to digital
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
28 - adi,ad7986
[all …]
Dadi,ad4000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4000-4004-4008.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4001-4005.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4003-4007-4011.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4020-4021-4022.pdf
20 https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4001.pdf
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
[all …]
/Documentation/devicetree/bindings/input/touchscreen/
Dgoodix,gt9916.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Neil Armstrong <neil.armstrong@linaro.org>
16 - $ref: touchscreen.yaml#
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
22 - goodix,gt9916
30 reset-gpios:
33 avdd-supply:
36 vddio-supply:
[all …]
Dcypress,cy8ctma340.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Javier Martinez Canillas <javier@dowhile0.org>
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: touchscreen.yaml#
26 - const: cypress,cy8ctma340
27 - const: cypress,cy8ctst341
28 - const: cypress,cyttsp-spi
31 - const: cypress,cyttsp-i2c
[all …]
Dbu21013.txt4 - compatible : "rohm,bu21013_tp"
5 - reg : I2C device address
6 - reset-gpios : GPIO pin enabling (selecting) chip (CS)
7 - interrupt-parent : the phandle for the gpio controller
8 - interrupts : (gpio) interrupt to which the chip is connected
11 - touch-gpios : GPIO pin registering a touch event
12 - <supply_name>-supply : Phandle to a regulator supply
13 - touchscreen-size-x : General touchscreen binding, see [1].
14 - touchscreen-size-y : General touchscreen binding, see [1].
15 - touchscreen-inverted-x : General touchscreen binding, see [1].
[all …]
/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
22 unused they can be left unconnected or remuxed to be used as GPIO or in some
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
[all …]
/Documentation/devicetree/bindings/regulator/
Ddlg,slg51000.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Jeong <eric.jeong.opensource@diasemi.com>
11 - Support Opensource <support.opensource@diasemi.com>
23 dlg,cs-gpios:
26 GPIO for chip select
28 vin3-supply:
32 vin4-supply:
36 vin5-supply:
[all …]

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