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/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.yaml41 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
113 qcom,xmem-recovery-cycles:
124 qcom,xmem-write-hold-cycles:
127 The extra cycles inserted after every write minimum 1. The
134 qcom,xmem-write-delta-cycles:
137 The initial latency for write cycles inserted for the first
142 qcom,xmem-read-delta-cycles:
145 The initial latency for read cycles inserted for the first
150 qcom,xmem-write-wait-cycles:
153 The number of wait cycles for every write access.
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Dnvidia,tegra20-gmi.txt56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr3.yaml46 of clock cycles.
53 SELF REFRESH) in terms of number of clock cycles.
60 cycles.
66 Four-bank activate window in terms of number of clock cycles.
72 Mode register set command delay in terms of number of clock cycles.
79 of clock cycles.
85 Row active time in terms of number of clock cycles.
91 ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
97 RAS-to-CAS delay in terms of number of clock cycles.
103 Refresh Cycle time in terms of number of clock cycles.
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Djedec,lpddr2.yaml53 Active bank a to active bank b in terms of number of clock cycles.
60 Internal WRITE-to-READ command delay in terms of number of clock cycles.
68 cycles. Obtained from device datasheet.
75 cycles. Obtained from device datasheet.
82 of clock cycles. Obtained from device datasheet.
88 Row precharge time (all banks) in terms of number of clock cycles.
95 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
102 WRITE recovery time in terms of number of clock cycles. Obtained from
109 Row active time in terms of number of clock cycles. Obtained from device
117 SELF REFRESH) in terms of number of clock cycles. Obtained from device
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/Documentation/devicetree/bindings/memory-controllers/
Dintel,ixp4xx-expansion-peripheral-props.yaml19 description: Address timing, extend address phase with n cycles.
24 description: Setup chip select timing, extend setup phase with n cycles.
29 description: Strobe timing, extend strobe phase with n cycles.
34 description: Hold timing, extend hold phase with n cycles.
39 description: Recovery timing, extend recovery phase with n cycles.
44 description: The type of cycles to use on the expansion bus for this
45 chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
70 description: Enable write cycles.
/Documentation/driver-api/mtd/
Dspi-nor.rst83 mode cycles 0
84 dummy cycles 0
87 mode cycles 0
88 dummy cycles 8
91 mode cycles 0
92 dummy cycles 8
95 mode cycles 4
96 dummy cycles 0
99 mode cycles 0
100 dummy cycles 8
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/Documentation/arch/m68k/
Dbuddha-driver.rst147 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
152 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
155 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
158 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
161 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
164 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
167 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
170 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
176 781ns select, IOR/IOW after 4 clock cycles (=314ns) active.
180 system: Sometimes two more clock cycles are inserted by the
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/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml81 mrvl,clk-delay-cycles:
82 description: Specify a number of cycles to delay for tuning.
105 mrvl,clk-delay-cycles = <31>;
117 mrvl,clk-delay-cycles = <0x1F>;
/Documentation/devicetree/bindings/misc/
Difm-csi.txt14 - ifm,csi-wait-cycles: sensor bus wait cycles
34 ifm,csi-wait-cycles = <0>;
/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos7-decon.yaml45 Clock cycles for the active period of address signal is enabled until
52 Clock cycles for the active period of CS is enabled.
58 Clock cycles for the active period of CS is disabled until write
65 Clock cycles for the active period of CS signal is enabled until
Dsamsung,fimd.yaml63 Clock cycles for the active period of address signal is enabled until
70 Clock cycles for the active period of CS is enabled.
76 Clock cycles for the active period of CS is disabled until write
83 Clock cycles for the active period of CS signal is enabled until
/Documentation/gpu/
Ddrm-usage-stats.rst103 - drm-cycles-<keystr>: <uint>
106 drm-engine-<keystr> tag and shall contain the number of busy cycles for the given
115 - drm-total-cycles-<keystr>: <uint>
118 drm-cycles-<keystr> tag and shall contain the total number cycles for the given
122 of drm-cycles-<keystr>. For drivers that implement this interface, the engine
132 engine. Taken together with drm-cycles-<keystr>, this can be used to calculate
137 A driver may implement either this key or drm-total-cycles-<keystr>, but not
Dpanfrost.rst26 drm-cycles-fragment: 1424359409
30 drm-cycles-vertex-tiler: 52617357
/Documentation/devicetree/bindings/cache/
Dbaikal,bt1-l2-ctl.yaml29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
/Documentation/misc-devices/
Disl29003.rst54 0: 2^16 cycles (default)
55 1: 2^12 cycles
56 2: 2^8 cycles
57 3: 2^4 cycles
/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt22 - ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
24 cycles for SR2_WTCNT_VALUE).
79 ti,clock-cycles = <8>;
99 ti,clock-cycles = <16>;
126 ti,clock-cycles = <16>;
/Documentation/ABI/testing/
Dsysfs-bus-iio-impedance-analyzer-ad593332 Number of output excitation cycles (settling time cycles)
Dsysfs-bus-event_source-devices-events5 /sys/devices/cpu/events/stalled-cycles-frontend
7 /sys/devices/cpu/events/stalled-cycles-backend
9 /sys/devices/cpu/events/cpu-cycles
Dsysfs-driver-panfrost-profiling6 Get/set drm fdinfo's engine and cycles profiling status.
/Documentation/devicetree/bindings/iio/adc/
Davia-hx711.yaml14 - sck-gpio gives a clock to the sensor with 24 cycles for data retrieval
15 and up to 3 cycles for selection of the input channel and gain for the
/Documentation/admin-guide/perf/
Dstarfive_starlink_pmu.rst32 starfive_starlink_pmu/cycles/ [Kernel PMU event]
43 $ perf stat -a -e /starfive_starlink_pmu/cycles/ sleep 1
/Documentation/staging/
Dstatic-keys.rst299 1,474,374,262 cycles # 1.723 GHz ( +- 0.17% )
300 <not supported> stalled-cycles-frontend
301 <not supported> stalled-cycles-backend
316 1,432,559,428 cycles # 1.703 GHz ( +- 0.18% )
317 <not supported> stalled-cycles-frontend
318 <not supported> stalled-cycles-backend
328 saved .2% on instructions, and 2.8% on cycles and 1.4% on elapsed time.
/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
161 * 2 pixclk cycles.
/Documentation/devicetree/bindings/ata/
Dsata_highbank.yaml32 Indicates the number of additional clock cycles to transmit before
38 Indicates the number of additional clock cycles to transmit after

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