Searched +full:d +full:- +full:tlb +full:- +full:size (Results 1 – 18 of 18) sorted by relevance
| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| D | dma-api-howto.rst | 10 with example pseudo-code. For a concise description of the API, see
11 Documentation/core-api/dma-api.rst.
23 The virtual memory system (TLB, page tables, etc.) translates virtual
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
49 +-------+ +------+ +------+
52 C +-------+ --------> B +------+ ----------> +------+ A
54 +-----+ | | | | bridge | | +--------+
55 | | | | +------+ | | | |
58 +-----+ +-------+ +------+ +------+ +--------+
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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| /Documentation/arch/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
11 we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
12 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
14 allow more flexible TLB handling for the future.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
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| /Documentation/arch/x86/ |
| D | pti.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 time. Once enabled at compile-time, it can be disabled at boot with
31 the 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
65 Protection against side-channel attacks is important. But,
70 a. Each process now needs an order-1 PGD instead of order-0.
72 b. The 'cpu_entry_area' structure must be 2MB in size and 2MB
89 feature of the MMU allows different processes to share TLB
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| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
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| /Documentation/virt/kvm/x86/ |
| D | mmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
17 a particular implementation such as tlb size)
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
12 LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`参考文献 <loongarch-references-zh_CN>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
56 ----------
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
12 LoongArch是一種新的RISC ISA，在一定程度上類似於MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`參考文獻 <loongarch-references-zh_TW>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 參數寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 臨時寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 靜態寄存器 是
56 ----------
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| /Documentation/driver-api/media/drivers/ |
| D | ipu6.rst | 1 .. SPDX-License-Identifier: GPL-2.0
34 ------------------------
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
98 page table entries for each DMA operation and invalidate the MMU TLB after each
101 .. code-block:: none
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| /Documentation/networking/ |
| D | bonding.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 Corrections, HA extensions: 2000/10/03-15:
13 - Willy Tarreau <willy at meta-x.org>
14 - Constantine Gavrilov <const-g at xpert.com>
15 - Chad N. Tindel <ctindel at ieee dot org>
16 - Janice Girouard <girouard at us dot ibm dot com>
17 - Jay Vosburgh <fubar at us dot ibm dot com>
22 - Mitch Williams <mitch.a.williams at intel.com>
35 the original tools from extreme-linux and beowulf sites will not work
119 -----------------------------------------------
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| /Documentation/driver-api/ |
| D | vfio.rst | 2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
12 safe [2]_, non-privileged, userspace drivers.
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
36 ---------------------------
42 as allowing a device read-write access to system memory imposes the
55 For instance, an individual device may be part of a larger multi-
59 could be anything from a multi-function PCI device with backdoors
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| /Documentation/filesystems/ |
| D | proc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 1.1 Process-Specific Subdirectories
36 3 Per-Process Parameters
37 3.1 /proc/<pid>/oom_adj & /proc/<pid>/oom_score_adj - Adjust the oom-killer
39 3.2 /proc/<pid>/oom_score - Display current oom-killer score
40 3.3 /proc/<pid>/io - Display the IO accounting fields
41 3.4 /proc/<pid>/coredump_filter - Core dump filtering settings
42 3.5 /proc/<pid>/mountinfo - Information about mounts
44 3.7 /proc/<pid>/task/<tid>/children - Information about task children
45 3.8 /proc/<pid>/fdinfo/<fd> - Information about opened file
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| /Documentation/arch/powerpc/ |
| D | ultravisor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
75 +---+---+---+---------------+
79 +---+---+---+---------------+
81 +---+---+---+---------------+
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| /Documentation/virt/kvm/ |
| D | api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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| /Documentation/RCU/ |
| D | RTFP.txt | 4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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