Home
last modified time | relevance | path

Searched +full:data +full:- +full:pins (Results 1 – 25 of 165) sorted by relevance

1234567

/Documentation/devicetree/bindings/iio/resolver/
Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
19 angular velocity data directly from the parallel outputs or through
23 selected by the A0 and A1 input pins. In normal mode, data is latched by
25 data is read or written using a register access scheme (address byte with
[all …]
/Documentation/driver-api/media/drivers/
Dbttv-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -------------------------
15 bttv-cards.c, which holds the information required for each board.
24 example. The file Documentation/admin-guide/media/bttv-cardlist.rst has a list
48 Below is a do-it-yourself description for you.
50 The bt8xx chips have 32 general purpose pins, and registers to control
51 these pins. One register is the output enable register
52 (``BT848_GPIO_OUT_EN``), it says which pins are actively driven by the
53 bt848 chip. Another one is the data register (``BT848_GPIO_DATA``), where
54 you can get/set the status if these pins. They can be used for input
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7606.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
22 - adi,ad7605-4
23 - adi,ad7606-4
[all …]
/Documentation/devicetree/bindings/net/
Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
[all …]
/Documentation/devicetree/bindings/sound/
Dcs53l30.txt5 - compatible : "cirrus,cs53l30"
7 - reg : the I2C address of the device
9 - VA-supply, VP-supply : power supplies for the device,
14 - reset-gpios : a GPIO spec for the reset pin.
16 - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either
20 - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin.
21 0 = Hi-Z
25 - cirrus,use-sdout2 : This is a boolean property. If present, it indicates
27 pins to output data. Otherwise, it indicates that
28 only SDOUT1 is connected for data output.
[all …]
Drt5640.txt7 - compatible : One of "realtek,rt5640" or "realtek,rt5639".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
15 - clocks: The phandle of the master clock to the CODEC
16 - clock-names: Should be "mclk"
18 - realtek,in1-differential
19 - realtek,in2-differential
20 - realtek,in3-differential
21 Boolean. Indicate MIC1/2/3 input are differential, rather than single-ended.
23 - realtek,lout-differential
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx27-pinctrl.txt4 - compatible: "fsl,imx27-iomuxc"
9 - fsl,pins: three integers array, represents a group of pins mux and config
10 setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
13 configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
21 0 - Primary function
22 1 - Alternate function
23 2 - GPIO
26 direction defines the data direction of the pin.
28 0 - Input
29 1 - Output
[all …]
Dqcom,sc7280-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 const: qcom,sc7280-lpass-lpi-pinctrl
24 "-state$":
26 - $ref: "#/$defs/qcom-sc7280-lpass-state"
27 - patternProperties:
28 "-pins$":
[all …]
Dqcom,sm6115-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Iskren Chernev <iskren.chernev@gmail.com>
18 const: qcom,sm6115-tlmm
23 reg-names:
25 - const: west
26 - const: south
27 - const: east
[all …]
Dqcom,sm8250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 const: qcom,sm8250-lpass-lpi-pinctrl
25 - description: LPASS Core voting clock
26 - description: LPASS Audio voting clock
28 clock-names:
30 - const: core
[all …]
Dqcom,sm4250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Audio voting clock
29 clock-names:
[all …]
Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
[all …]
Dqcom,qcm2290-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
17 const: qcom,qcm2290-tlmm
26 "-state$":
28 - $ref: "#/$defs/qcom-qcm2290-tlmm-state"
29 - patternProperties:
30 "-pins$":
[all …]
Dqcom,msm8974-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8974-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
Dqcom,sm8450-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
[all …]
Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
[all …]
Dqcom,sm6125-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Martin Botka <martin.botka@somainline.org>
15 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19 const: qcom,sm6125-tlmm
24 reg-names:
26 - const: west
27 - const: south
[all …]
Dqcom,msm8998-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8998-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8998-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
5 The TDA19971 Video port output pins can be used as follows:
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
[all …]
/Documentation/devicetree/bindings/mtd/
Dgpio-control-nand.txt4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to the NAND flash and all accesses
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
24 the GPIO's and the NAND flash data bus. If present, then after changing
[all …]
/Documentation/hwmon/
Dpcf8591.rst17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
35 - mode 1 : three differential inputs
36 Pins AIN3 is the common negative differential input
[all …]
Ducd9000.rst11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd90120.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd90124.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd90160.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd90320.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9090.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd90910.pdf
22 Author: Guenter Roeck <linux@roeck-us.net>
26 -----------
31 sequences up to 12 independent voltage rails. The device integrates a 12-bit
[all …]
/Documentation/driver-api/gpio/
Dboard.rst11 tree, ACPI, and platform data.
14 -----------
20 <function>-gpios, where <function> is the function the driver will request
26 led-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>, /* red */
30 power-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
33 Properties named <function>-gpio are also considered valid and old bindings use
52 the <function>-prefix of the GPIO suffixes ("gpios" or "gpio", automatically
54 "led-gpios" example, use the prefix without the "-" as con_id parameter: "led".
58 (``snprintf(... "%s-%s", con_id, gpio_suffixes[]``).
61 ----
[all …]

1234567