Searched +full:ddr +full:- +full:wb +full:- +full:channels (Results 1 – 2 of 2) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | qca,ath79-cpu-intc.txt | 3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
29 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | qca,ath79-ddr-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
21 - items:
22 - const: qca,ar9132-ddr-controller
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