| /Documentation/devicetree/bindings/perf/ |
| D | fsl-imx-ddr.yaml | 4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr-pmu
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| D | amlogic,g12-ddr-pmu.yaml | 4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
49 compatible = "amlogic,g12a-ddr-pmu";
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| D | marvell-cn10k-ddr.yaml | 4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
7 title: Marvell CN10K DDR performance monitor
16 - marvell,cn10k-ddr-pmu
34 compatible = "marvell,cn10k-ddr-pmu";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | brcm,brcmstb-memc-ddr.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
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| D | qca,ath79-ddr-controller.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr-wb-channel-cells"
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| D | calxeda-ddr-ctrlr.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
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| D | xlnx,versal-ddrmc-edac.yaml | 7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
24 - description: DDR Memory Controller registers
25 - description: NOC registers corresponding to DDR Memory Controller
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| D | snps,dw-umctl2-ddrc.yaml | 14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
27 description: Synopsys DW uMCTL2 DDR controller v3.80a
29 - description: Synopsys DW uMCTL2 DDR controller
31 - description: Xilinx ZynqMP DDR controller v2.40a
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| D | rockchip,rk3399-dmc.yaml | 20 Node to get DDR loading. Refer to
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
51 For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
318 Defines the power-down idle disable frequency in Hz. When the DDR
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
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| /Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | qca,ath79-cpu-intc.txt | 3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
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| /Documentation/devicetree/bindings/clock/ |
| D | amlogic,meson8-ddr-clkc.yaml | 4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
7 title: Amlogic DDR Clock Controller
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
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| D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
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| D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
20 - clock-output-names: should be "cpu", "ddr", "ahb"
32 clock-output-names = "cpu", "ddr", "ahb";
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| D | microchip,lan966x-gck.yaml | 30 - description: DDR clock source
36 - const: ddr
57 clock-names = "cpu", "ddr", "sys";
|
| /Documentation/ABI/testing/ |
| D | sysfs-driver-bd9571mwv-regulator | 5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
10 A. With a momentary power switch (or pulse signal), DDR
26 DDR Backup Mode must be explicitly enabled by the user,
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| D | sysfs-platform-brcmstb-memc | 7 internal DDR controller clock cycles. Possible values range
15 DDR PHY frequency in Hz.
|
| /Documentation/admin-guide/perf/ |
| D | meson-ddr-pmu.rst | 4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
24 Below are DDR access request event filter keywords:
55 + Show the total DDR bandwidth per seconds:
62 + Show individual DDR bandwidth from CPU and GPU respectively, as well as
|
| D | alibaba_pmu.rst | 9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
43 The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
44 for connecting an SoC application bus to DDR memory devices. The DDRCTL
49 the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
|
| D | index.rst | 13 imx-ddr
26 meson-ddr-pmu
|
| /Documentation/driver-api/thermal/ |
| D | intel_dptf.rst | 198 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
219 DRAM devices of DDR IO interface and their power plane can generate EMI
221 mechanism by which DDR data rates can be changed if several conditions
222 are met: there is strong RFI interference because of DDR; CPU power
223 management has no other restriction in changing DDR data rates;
224 PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
225 DDR-RFIM) for Wi-Fi from BIOS.
259 Request the restriction of specific DDR data rate and set this
267 Restricted DDR data rate for RFI protection: Lower Limit
270 Restricted DDR data rate for RFI protection: Upper Limit
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| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd9576-pmic.yaml | 47 rohm,ddr-sel-low:
49 The BD9576 and BD9573 output voltage for DDR can be selected by setting
50 the ddr-sel pin low or high. Set this property if ddr-sel is grounded.
97 rohm,ddr-sel-low;
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| D | rohm,bd9571mwv.yaml | 34 rohm,ddr-backup-power:
39 Value to use for DDR-Backup Power (default 0).
40 This is a bitmask that specifies which DDR power rails need to be kept
114 rohm,ddr-backup-power = <0xf>;
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr-channel.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
80 $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
98 $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
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