Searched full:ddrc (Results 1 – 7 of 7) sorted by relevance
| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | imx8m-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
64 ddrc: memory-controller@3d400000 {
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
28 const: snps,ddrc-3.80a
30 const: snps,dw-umctl2-ddrc
32 const: xlnx,zynqmp-ddrc-2.40a
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
61 reference clock, DDRC core clock, Scrubber standalone clock
62 (synchronous to the DDRC clock).
96 compatible = "xlnx,zynqmp-ddrc-2.40a";
107 compatible = "snps,dw-umctl2-ddrc";
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| D | xlnx,zynq-ddrc-a05.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
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| /Documentation/devicetree/bindings/interconnect/ |
| D | fsl,imx8m-noc.yaml | 53 fsl,ddrc:
81 fsl,ddrc = <&ddrc>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
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| /Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
20 HHA and DDRC etc. The available events and configuration options shall
23 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
26 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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| D | alibaba_pmu.rst | 28 based on DDRC core clock.
53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra20-pinmux.yaml | 47 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
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