Searched full:defines (Results 1 – 25 of 507) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 60 Configure the PD_IDLE value. Defines the power-down idle period in which
69 Configure the SR_IDLE value. Defines the self-refresh idle period in
79 Defines the memory self-refresh and controller clock gating idle period.
89 Defines the self-refresh power down idle period in which memories are
99 Defines the standby idle period in which memories are placed into
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
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| D | st,stm32-fmc2-ebi-props.yaml | 89 description: This property defines the duration of the address setup
93 description: This property defines the duration of the address hold
98 description: This property defines the duration of the data setup phase
102 description: This property defines the delay in nanoseconds between the
106 description: This property defines the duration of the data hold phase
110 description: This property defines the FMC_CLK output signal period in
114 description: This property defines the data latency before reading or
118 description: This property defines the duration of the address setup
122 description: This property defines the duration of the address hold
127 description: This property defines the duration of the data setup
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| D | mvebu-devbus.txt | 37 - devbus,turn-off-ps: Defines the time during which the controller does not
43 - devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
52 - devbus,acc-first-ps: Defines the time delay from the negation of
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
62 - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
71 - devbus,rd-hold-ps: Defines the time between the last data sample to the
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
89 - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
91 is active. This parameter defines the setup time of
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | cpus.txt | 17 Freescale Power Architecture) defines the architecture for Freescale
18 Power CPUs. The EREF defines some architecture categories not defined
32 snooped. This property defines a bitmask which selects the bit
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-funnel | 5 Description: (RW) Enables the slave ports and defines the hold time of the
12 Description: (RW) Defines input port priority order.
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| D | sysfs-bus-event_source-devices-format | 8 Each attribute of this group defines the 'hardware' bitmask
20 Defines contents of attribute that occupies bits 1,6-10,44 of
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| D | sysfs-bus-coresight-devices-etm3x | 119 Description: (RW) Defines which event triggers a trace.
177 Description: (RW) Defines the event that causes the sequencer to transition
184 Description: (RW) Defines the event that causes the sequencer to transition
191 Description: (RW) Defines the event that causes the sequencer to transition
198 Description: (RW) Defines the event that causes the sequencer to transition
205 Description: (RW) Defines the event that causes the sequencer to transition
212 Description: (RW) Defines the event that causes the sequencer to transition
232 Description: (RW) Defines an event that requests the insertion of a timestamp
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| /Documentation/devicetree/bindings/extcon/ |
| D | wlf,arizona.yaml | 65 detection, specified as per the ARIZONA_MICD_TIME_XXX defines.
73 as per the ARIZONA_MICD_TIME_XXX defines.
104 The first cell defines the accessory detection pin, zero
121 ARIZONA_GPSW_XXX defines.
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| /Documentation/devicetree/bindings/leds/ |
| D | richtek,rt8515.yaml | 36 defines the range of the dimmer setting (brightness) of the
45 defines the range of the dimmer setting (brightness) of the
66 to be defined as it defines the maximum range.
78 to be defined as it defines the maximum range.
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| /Documentation/userspace-api/media/ |
| D | ca.h.rst.exceptions | 6 # struct ca_slot_info defines
15 # struct ca_descr_info defines
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| /Documentation/sphinx/ |
| D | parse-headers.pl | 25 my %defines;
84 $defines{$s} = "\\ :ref:`$s <$n>`\\ ";
157 delete $defines{$1} if (exists($defines{$1}));
204 $defines{$old} = $new if (exists($defines{$old}));
233 print Data::Dumper->Dump([\%defines], [qw(*defines)]) if (%defines);
270 foreach my $r (keys %defines) {
271 my $s = $defines{$r};
341 enums and defines and create cross-references to a Sphinx book.
377 It is capable of identifying defines, functions, structs, typedefs,
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| /Documentation/driver-api/rapidio/ |
| D | tsi721.rst | 33 - This parameter defines number of hardware buffer
38 - DMA transactions queue size. Defines number of pending
43 - DMA channel selection mask. Bitmask that defines which hardware
58 - RIO messaging MBOX selection mask. This is a bitmask that defines
84 - defines number of hardware buffer descriptors used by
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| /Documentation/devicetree/bindings/gpio/ |
| D | 8xxx_gpio.txt | 34 - #interrupt-cells: Should be two. Defines the number of integer
37 defines the pin number, the second cell
38 defines additional flags (trigger type,
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| /Documentation/userspace-api/media/v4l/ |
| D | colorspaces.rst | 12 you can accurately display that color. A colorspace defines what it
40 standard that defines spectral weighting functions that model the
41 perception of color. Specifically that standard defines functions that
72 defines a colorspace.
95 intensity of the color. So each colorspace also defines a transfer
105 The final piece that defines a colorspace is a function that transforms
148 colorspace standard only defines some, and you have to rely on other
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | nxp,tda998x.yaml | 27 24 bits value which defines how the video controller output is wired to
41 The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S
45 The second value defines the tda998x AP_ENA reg content when the
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ltc2990.txt | 9 The first integer defines the bits 2..0 in the control register. In all
22 The second integer defines the bits 4..3 in the control register. This
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| /Documentation/devicetree/bindings/sound/ |
| D | mvebu-audio.txt | 24 The first one is mandatory and defines the internal clock.
25 The second one is optional and defines an external clock.
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| D | cirrus,cs42l42.yaml | 70 The CS42L42_TS_INV_* defines are available for this.
89 The CS42L42_TS_DBNCE_* defines are available for this.
108 The CS42L42_TS_DBNCE_* defines are available for this.
171 The CS42L42_HSBIAS_RAMP_* defines are available for this.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | mediatek,mt8192-pinctrl.yaml | 93 defines in dt-bindings/pinctrl/mt65xx.h.
95 description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines
104 defines in dt-bindings/pinctrl/mt65xx.h.
106 description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines
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| /Documentation/devicetree/bindings/phy/ |
| D | mscc,vsc7514-serdes.yaml | 40 The first number defines the input port to use for a given SerDes macro.
41 The second defines the macro to use. They are defined in
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec6.txt | 13 Node defines the base address of the SEC 6 block.
34 Definition: A standard property. Defines the number of cells
40 Definition: A standard property. Defines the number of cells
74 Child of the crypto node defines data processing interface to SEC 6
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| D | fsl,sec-v4.0.yaml | 79 description: Defines the 'ERA' of the SEC device.
87 Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
124 Run Time Integrity Check (RTIC) Node. Defines a register space that
162 Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
164 memory areas that should not modified. The node defines a register
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| /Documentation/devicetree/bindings/display/panel/ |
| D | panel-mipi-dbi-spi.yaml | 16 The MIPI Alliance Standard for Display Bus Interface defines the electrical
18 phones. The standard defines 4 display architecture types and this binding is
22 The standard defines the following interface signals for type C:
53 The standard defines one pixel format for type C: RGB111. The industry
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| /Documentation/core-api/ |
| D | netlink.rst | 70 Defines whether the kernel validation policy is ``global`` i.e. the same for all
90 Defines max length for a binary or string attribute (corresponding
102 Similar to ``max-len`` but defines minimum length.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-lapic.yaml | 26 This schema defines bindings for local APIC interrupt controller.
43 description: Intel defines a few possible interrupt delivery
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