Searched full:delay (Results 1 – 25 of 436) sorted by relevance
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| /Documentation/accounting/ |
| D | delay-accounting.rst | 2 Delay accounting
9 The per-task delay accounting functionality measures
29 delay statistics aggregated for all tasks (or threads) belonging to a
34 aggregate delay statistics into arbitrary groups. To enable this, delay
42 Delay accounting uses the taskstats interface which is described
45 statistics. The delay accounting functionality populates specific fields of
50 for a description of the fields pertaining to delay accounting.
52 delay seen for cpu, sync block I/O, swapin, memory reclaim, thrash page
56 counter (say cpu_delay_total) for a task will give the delay
66 commands to be run and the corresponding delay statistics to be displayed. It
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| D | taskstats-struct.rst | 13 2) Delay accounting fields
16 /* Delay accounting fields start */
20 /* Delay accounting fields end */
38 6) Extended delay accounting fields for memory reclaim
97 2) Delay accounting fields::
99 /* Delay accounting fields start
101 * All values, until the comment "Delay accounting fields end" are
102 * available only if delay accounting is enabled, even though the last
105 * xxx_count is the number of delay values recorded
106 * xxx_delay_total is the corresponding cumulative delay in nanoseconds
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| /Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 35 # They are used to delay the data valid window, and align the window to
36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
39 cdns,phy-input-delay-sd-highspeed:
40 description: Value of the delay in the input path for SD high-speed timing
45 cdns,phy-input-delay-legacy:
46 description: Value of the delay in the input path for legacy timing
51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the input path for SD UHS SDR12 timing
57 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the input path for SD UHS SDR25 timing
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| D | sdhci-am654.yaml | 57 # Used to delay the data valid window and align it to the sampling clock.
62 description: Output tap delay for SD/MMC legacy timing
68 description: Output tap delay for MMC high speed timing
74 description: Output tap delay for SD high speed timing
80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
98 description: Output tap delay for SD UHS SDR104 timing
104 description: Output tap delay for SD UHS DDR50 timing
110 description: Output tap delay for eMMC DDR52 timing
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| D | sprd,sdhci-r11.yaml | 53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":
56 - description: clock data write line delay value
57 - description: clock read command line delay value
58 - description: clock read data positive edge delay value
59 - description: clock read data negative edge delay value
61 PHY DLL delays are used to delay the data valid window, and align
62 the window to the sampling clock. Each cell's delay value unit is
107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
108 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
109 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
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| D | fsl-imx-esdhc.yaml | 109 fsl,delay-line:
112 Specify the number of delay cells for override mode.
113 This is used to set the clock delay for DLL(Delay Line) on override mode
116 chapter, DLL (Delay Line) section in RM for details.
135 Specify the start delay cell point when send first CMD19 in tuning procedure.
141 Specify the increasing delay cell steps in tuning procedure.
142 The uSDHC use one delay cell as default increasing step to do tuning process.
143 This property allows user to change the tuning step to more than one delay
145 tuning step can't find the proper delay window within limited tuning retries.
148 fsl,strobe-dll-delay-target:
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| /Documentation/translations/zh_CN/accounting/ |
| D | delay-accounting.rst | 3 :Original: Documentation/accounting/delay-accounting.rst
92 CPU count real total virtual total delay total delay average
94 IO count delay total delay average
96 SWAP count delay total delay average
98 RECLAIM count delay total delay average
100 THRASHING count delay total delay average
102 COMPACT count delay total delay average
104 WPCOPY count delay total delay average
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| /Documentation/devicetree/bindings/regulator/ |
| D | mediatek,mt6397-regulator.yaml | 77 regulator-ramp-delay = <12500>;
78 regulator-enable-ramp-delay = <200>;
85 regulator-ramp-delay = <12500>;
86 regulator-enable-ramp-delay = <115>;
93 regulator-ramp-delay = <12500>;
94 regulator-enable-ramp-delay = <115>;
101 regulator-ramp-delay = <12500>;
102 regulator-enable-ramp-delay = <115>;
109 regulator-ramp-delay = <12500>;
110 regulator-enable-ramp-delay = <115>;
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| D | mediatek,mt6357-regulator.yaml | 80 regulator-ramp-delay = <6250>;
81 regulator-enable-ramp-delay = <220>;
88 regulator-ramp-delay = <6250>;
89 regulator-enable-ramp-delay = <220>;
96 regulator-ramp-delay = <6250>;
97 regulator-enable-ramp-delay = <220>;
103 regulator-ramp-delay = <12500>;
104 regulator-enable-ramp-delay = <220>;
111 regulator-ramp-delay = <50000>;
112 regulator-enable-ramp-delay = <220>;
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| D | mt6323-regulator.txt | 27 regulator-ramp-delay = <12500>;
36 regulator-ramp-delay = <25000>;
51 regulator-enable-ramp-delay = <90>;
60 regulator-enable-ramp-delay = <185>;
67 regulator-enable-ramp-delay = <185>;
74 regulator-enable-ramp-delay = <185>;
81 regulator-enable-ramp-delay = <216>;
90 regulator-enable-ramp-delay = <216>;
97 regulator-enable-ramp-delay = <216>;
106 regulator-enable-ramp-delay = <216>;
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| D | mt6359-regulator.yaml | 111 regulator-enable-ramp-delay = <0>;
118 regulator-ramp-delay = <5000>;
119 regulator-enable-ramp-delay = <200>;
126 regulator-ramp-delay = <10760>;
127 regulator-enable-ramp-delay = <200>;
133 regulator-ramp-delay = <5000>;
134 regulator-enable-ramp-delay = <200>;
141 regulator-ramp-delay = <5000>;
142 regulator-enable-ramp-delay = <200>;
149 regulator-enable-ramp-delay = <0>;
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| /Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.yaml | 23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
24 active->inactive edge, triggering negative edge triggered reset. After a delay specified by
25 inactive-delay, the GPIO is driven active again. After a delay specified by wait-delay, the
49 active-delay:
51 description: Delay (default 100) to wait after driving gpio active [ms]
54 inactive-delay:
56 description: Delay (default 100) to wait after driving gpio inactive [ms]
59 wait-delay:
61 description: Delay (default 3000) to wait after completing restart sequence [ms]
76 active-delay = <100>;
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| D | gpio-poweroff.yaml | 15 from inactive to active. After a delay (active-delay-ms) it
17 delay (inactive-delay-ms) it is configured as active again.
38 active-delay-ms:
40 description: Delay to wait after driving gpio active
42 inactive-delay-ms:
44 description: Delay to wait after driving gpio inactive
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| /Documentation/devicetree/bindings/thermal/ |
| D | brcm,sr-thermal.txt | 11 - polling-delay: Max number of milliseconds to wait between polls.
34 polling-delay-passive = <0>;
35 polling-delay = <1000>;
46 polling-delay-passive = <0>;
47 polling-delay = <1000>;
58 polling-delay-passive = <0>;
59 polling-delay = <1000>;
70 polling-delay-passive = <0>;
71 polling-delay = <1000>;
82 polling-delay-passive = <0>;
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 67 - mpmc,write-enable-delay: Delay from chip select assertion to write
70 - mpmc,output-enable-delay: Delay from chip select assertion to output
73 - mpmc,write-access-delay: Delay from chip select assertion to write
76 - mpmc,read-access-delay: Delay from chip select assertion to read
79 - mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
82 - mpmc,turn-round-delay: Delay between access to memory banks in nano
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
112 mpmc,read-enable-delay = <70>;
113 mpmc,page-mode-read-delay = <70>;
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 12 controller specific like delay in clock or data lines, etc. These properties
47 spi-cs-setup-delay-ns:
49 Delay in nanoseconds to be introduced by the controller after CS is
52 spi-cs-hold-delay-ns:
54 Delay in nanoseconds to be introduced by the controller before CS is
57 spi-cs-inactive-delay-ns:
59 Delay in nanoseconds to be introduced by the controller after CS is
70 spi-rx-delay-us:
72 Delay, in microseconds, after a read transfer.
74 rx-sample-delay-ns:
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| D | cdns,qspi-nor-peripheral-props.yaml | 17 cdns,read-delay:
20 Delay for read capture logic, in clock cycles.
24 Delay in nanoseconds for the length that the master mode chip select
29 Delay in nanoseconds between one chip select being de-activated
34 Delay in nanoseconds between last bit of current transaction and
39 Delay in nanoseconds between setting qspi_n_ss_out low and
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| /Documentation/admin-guide/device-mapper/ |
| D | delay.rst | 2 dm-delay
5 Device-Mapper's "delay" target delays reads and/or writes
10 <device> <offset> <delay> [<write_device> <write_offset> <write_delay>
15 3: apply offset and delay to read, write and flush operations on device
17 6: apply offset and delay to device, also apply write_offset and write_delay
37 dmsetup create delayed --table "0 `blockdev --getsz $1` delay $1 0 500"
46 dmsetup create delayed --table "0 `blockdev --getsz $1` delay $1 2048 0 $2 4096 400"
54 dmsetup create delayed --table "0 `blockdev --getsz $1` delay $1 0 50 $2 0 100 $1 0 333"
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | nxp,sja1105.yaml | 93 rx-internal-delay-ps:
94 $ref: "#/$defs/internal-delay-ps"
95 tx-internal-delay-ps:
96 $ref: "#/$defs/internal-delay-ps"
103 internal-delay-ps:
105 Disable tunable delay lines using 0 ps, or enable them and select
157 rx-internal-delay-ps = <0>;
158 tx-internal-delay-ps = <0>;
165 rx-internal-delay-ps = <0>;
166 tx-internal-delay-ps = <0>;
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| /Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.yaml | 31 power-on-delay:
32 description: delay after turning regulators on [ms]
35 reset-delay:
36 description: delay after reset sequence [ms]
39 init-delay:
40 description: delay after initialization sequence [ms]
79 power-on-delay = <50>;
80 reset-delay = <100>;
81 init-delay = <100>;
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| /Documentation/devicetree/bindings/net/ |
| D | amlogic,meson-dwmac.yaml | 60 amlogic,tx-delay-ns:
64 The internal RGMII TX clock delay (provided by this driver)
66 delay should be explicitly configured. When the phy-mode is
67 set to either "rgmii-id" or "rgmii-txid" the TX clock delay
69 should be set to 0ns (which disables the TX clock delay in
71 PHY and MAC are adding a delay). Any configuration is
74 amlogic,rx-delay-ns:
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
82 rx-internal-delay-ps instead.
84 rx-internal-delay-ps:
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| D | mdio.yaml | 36 reset-delay-us:
42 reset-post-delay-us:
44 Delay after reset deassert in microseconds. It applies to all MDIO
46 communication. This delay happens just before e.g. Ethernet PHY
86 Delay after the reset was asserted in microseconds. If this
87 property is missing the delay will be skipped.
91 Delay after the reset was deasserted in microseconds. If
92 this property is missing the delay will be skipped.
107 reset-delay-us = <2>;
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| D | adi,adin.yaml | 19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
68 adi,rx-internal-delay-ps = <1800>;
69 adi,tx-internal-delay-ps = <2200>;
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| /Documentation/devicetree/bindings/sound/ |
| D | dmic-codec.yaml | 33 modeswitch-delay-ms:
34 description: Delay (in ms) to complete DMIC mode switch
36 wakeup-delay-ms:
37 description: Delay (in ms) after enabling the DMIC
52 wakeup-delay-ms = <50>;
53 modeswitch-delay-ms = <35>;
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| /Documentation/devicetree/bindings/mtd/ |
| D | cadence-nand-controller.txt | 17 - cdns,board-delay-ps : Estimated Board delay. The value includes the total
18 round trip delay for the signals and is used for deciding on values
21 board delay = RE#PAD delay + PCB trace to device + PCB trace from device
22 + DQ PAD delay
42 cdns,board-delay-ps = <4830>;
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