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/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
/Documentation/devicetree/bindings/net/
Dallwinner,sun4i-a10-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun4i-a10-emac
29 allwinner,sram:
30 description: Phandle to the device SRAM
[all …]
Dmarvell-neta-bm.txt5 - compatible: should be "marvell,armada-380-neta-bm".
6 - reg: address and length of the register set for the device.
7 - clocks: a pointer to the reference clock for this device.
8 - internal-mem: a phandle to BM internal SRAM definition.
12 - pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
17 - pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
23 refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.
27 - main node:
30 compatible = "marvell,armada-380-neta-bm";
33 internal-mem = <&bm_bppi>;
[all …]
Dlpc-eth.txt4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
26 phy-mode = "rmii";
27 use-iram;
/Documentation/devicetree/bindings/media/
Dallwinner,sun4i-a10-video-engine.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
19 - allwinner,sun8i-a33-video-engine
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
[all …]
Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
25 host processor (Arm CorePac) to perform the device management of the remote
[all …]
Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
27 Each Dual-Core R5F sub-system is represented as a single DTS node
[all …]
/Documentation/devicetree/bindings/memory-controllers/ti/
Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
29 - interrupts : interrupt used by the controller
[all …]
/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
29 the system SRAM) for different peripheral. It can access external RAMs but
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
[all …]
/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
[all …]
Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
21 the device tree.
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
[all …]
Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
19 the SCPI provide for OSPM in the device tree.
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
35 - items:
36 - enum:
37 - amlogic,meson-gxbb-scpi
[all …]
/Documentation/devicetree/bindings/bus/
Dallwinner,sun50i-a64-de2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 pattern: "^bus(@[0-9a-f]+)?$"
17 "#address-cells":
20 "#size-cells":
25 - const: allwinner,sun50i-a64-de2
[all …]
/Documentation/devicetree/bindings/fsi/
Dfsi-master-ast-cf.txt1 Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
2 ------------------------------------------------------------------------
5 - compatible =
6 "aspeed,ast2400-cf-fsi-master" for an AST2400 based system
8 "aspeed,ast2500-cf-fsi-master" for an AST2500 based system
10 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
11 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
12 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
13 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
14 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
[all …]
Darm,pl35x-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 SRAM or NOR) depending on the specific configuration.
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
27 - arm,pl354
29 - compatible
[all …]
/Documentation/devicetree/bindings/mtd/
Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
[all …]
Dmicrochip,mchp23k256.txt1 * MTD SPI driver for Microchip 23K256 (and similar) serial SRAM
4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : Must be one of "microchip,mchp23k256" or "microchip,mchp23lcv1024"
7 - reg : Chip-Select number
8 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
12 spi-sram@0 {
13 #address-cells = <1>;
14 #size-cells = <1>;
17 spi-max-frequency = <20000000>;
Darm,pl353-nand-r2p1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml
13 - Miquel Raynal <miquel.raynal@bootlin.com>
18 - const: arm,pl353-nand-r2p1
22 - items:
23 - description: CS with regard to the parent ranges property
24 - description: Offset of the memory region requested by the device
[all …]
/Documentation/devicetree/bindings/usb/
Dallwinner,sun4i-a10-musb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/allwinner,sun4i-a10-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun4i-a10-musb
18 - allwinner,sun6i-a31-musb
19 - allwinner,sun8i-a33-musb
[all …]
/Documentation/devicetree/bindings/mailbox/
Dhisilicon,hi6220-mailbox.txt9 Mailbox Device Node:
13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
28 - interrupts: Contains the interrupt information for the mailbox
29 device. The format is dependent on which interrupt
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
40 --------
[all …]
/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
93 0x00000001 (bit 0) - mode:
[all …]
/Documentation/devicetree/bindings/mfd/
Datmel-smc.txt1 * Device tree bindings for Atmel SMC (Static Memory Controller)
4 to interface with standard memory devices (NAND, NOR, SRAM or specialized
8 - compatible: Should be one of the following
9 "atmel,at91sam9260-smc", "syscon"
10 "atmel,sama5d3-smc", "syscon"
11 "atmel,sama5d2-smc", "syscon"
12 "microchip,sam9x60-smc", "syscon"
13 "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"
14 - reg: Contains offset/length value of the SMC memory
20 compatible = "atmel,sama5d3-smc", "syscon";
/Documentation/devicetree/bindings/display/msm/
Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
30 figure out the chip-id.
[all …]

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