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/Documentation/ABI/testing/
Dsysfs-driver-typec-displayport1 What: /sys/bus/typec/devices/.../displayport/configuration
5 Shows the current DisplayPort configuration for the connector.
6 Valid values are USB, source and sink. Source means DisplayPort
7 source, and sink means DisplayPort sink.
19 separate configuration defined in VESA DisplayPort Alt Mode on
25 What: /sys/bus/typec/devices/.../displayport/pin_assignment
29 VESA DisplayPort Alt Mode on USB Type-C Standard defines six
44 Note. As of VESA DisplayPort Alt Mode on USB Type-C Standard
49 for carrying DisplayPort protocol (allowing higher resolutions).
51 What: /sys/bus/typec/devices/.../displayport/hpd
[all …]
/Documentation/devicetree/bindings/clock/
Dqcom,dispcc-sc8280xp.yaml30 - description: DisplayPort 0 link clock
31 - description: DisplayPort 0 VCO div clock
32 - description: DisplayPort 1 link clock
33 - description: DisplayPort 1 VCO div clock
34 - description: DisplayPort 2 link clock
35 - description: DisplayPort 2 VCO div clock
36 - description: DisplayPort 3 link clock
37 - description: DisplayPort 3 VCO div clock
Dqcom,mmcc.yaml298 - description: DisplayPort phy PLL link clock
299 - description: DisplayPort phy PLL vco clock
334 - description: DisplayPort phy PLL link clock
335 - description: DisplayPort phy PLL vco clock
/Documentation/userspace-api/media/v4l/
Dext-ctrls-dv.rst12 (Digital Visual Interface), HDMI (:ref:`hdmi`) and DisplayPort
47 read-only control is applicable to DVI-D, HDMI and DisplayPort
65 is applicable to VGA, DVI-A/D, HDMI and DisplayPort connectors.
89 DVI-A/D, HDMI and DisplayPort connectors.
96 information is sent over HDMI and DisplayPort connectors as part of
133 DisplayPort connectors.
148 DVI-A/D, HDMI and DisplayPort connectors.
155 sent over HDMI and DisplayPort connectors as part of the AVI
/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines based on the DisplayPort v1.2
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
33 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34 Source Controller handles the DisplayPort protocol and connects to external
123 Connections to the programmable logic and the DisplayPort PHYs. Each port
149 description: The DisplayPort output
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra124-dpaux.yaml7 title: NVIDIA Tegra DisplayPort AUX Interface
18 When configured for DisplayPort AUX operation, the DPAUX controller
19 can also be used to communicate with a DisplayPort device using the
76 description: phandle of a supply that powers the DisplayPort
/Documentation/devicetree/bindings/display/
Ddp-aux-bus.yaml7 title: DisplayPort AUX bus
13 DisplayPort controllers provide a control channel to the sinks that
/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dpdma.yaml7 title: Xilinx ZynqMP DisplayPort DMA Controller
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
/Documentation/devicetree/bindings/display/bridge/
Dparade,ps8622.yaml7 title: Parade PS8622/PS8625 DisplayPort to LVDS Converter
50 description: Video port for DisplayPort input.
Dite,it6505.yaml16 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
17 fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
Dgoogle,cros-ec-anx7688.yaml14 DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
Danalogix,anx7814.yaml58 Video port for SlimPort, DisplayPort, eDP or MyDP output.
/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort interface specification.
185 displayport-controller@ae90000 {
Dqcom,x1e80100-mdss.yaml45 "^displayport-controller@[0-9a-f]+$":
171 displayport-controller@ae90000 {
/Documentation/devicetree/bindings/display/connector/
Ddp-connector.yaml7 title: DisplayPort Connector
/Documentation/devicetree/bindings/phy/
Dsamsung,dp-video-phy.yaml7 title: Samsung Exynos SoC DisplayPort PHY
Dphy-rockchip-usbdp.yaml57 determines the DisplayPort (DP) lane index, while the value of an entry
64 DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
Dphy-cadence-torrent.yaml11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
123 Maximum DisplayPort link bit rate to use, in Mbps
/Documentation/admin-guide/media/
Dcec.rst26 - DisplayPort CEC-Tunneling-over-AUX on i915, nouveau and amdgpu
95 DisplayPort to HDMI Adapters with working CEC
130 DisplayPort to HDMI
135 CableCreation (SKU: CD0712): https://www.cablecreation.com/products/active-displayport-to-hdmi-adap…
137 HP DisplayPort to HDMI True 4k Adapter (P/N 2JA63AA): https://www.hp.com/us-en/shop/pdp/hp-displayp…
139 Mini-DisplayPort to HDMI
/Documentation/devicetree/bindings/usb/
Dnxp,ptn36502.yaml7 title: NXP PTN36502 Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst114 DisplayPort Configuration Data
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dpi.yaml82 attached HDMI, LVDS or DisplayPort encoder chip.
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,pmic-glink.yaml18 particularly the USB Type-C controllers relationship with USB and DisplayPort
/Documentation/devicetree/bindings/display/sprd/
Dsprd,display-subsystem.yaml37 | +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1|
/Documentation/gpu/
Dtegra.rst22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
132 panel for notebook form factors. Tegra210 added support for full DisplayPort

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