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/Documentation/devicetree/bindings/dma/
Dqcom,gpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
22 - enum:
23 - qcom,sdm845-gpi-dma
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Dbrcm,bcm2835-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 DMA controller
10 - Nicolas Saenz Julienne <nsaenz@kernel.org>
13 The BCM2835 DMA controller has 16 channels in total. Only the lower
19 - $ref: dma-controller.yaml#
23 const: brcm,bcm2835-dma
30 Should contain the DMA interrupts associated to the DMA channels in
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Dnvidia,tegra186-gpc-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPC DMA Controller
10 The Tegra General Purpose Central (GPC) DMA controller is used for faster
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Rajesh Gumasta <rgumasta@nvidia.com>
19 - $ref: dma-controller.yaml#
24 - const: nvidia,tegra186-gpcdma
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Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lightning Mountain centralized DMA controllers.
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
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Ddma-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Engine Common Properties
10 - Vinod Koul <vkoul@kernel.org>
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
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Dti-edma.txt3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
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Dnvidia,tegra210-adma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Audio DMA (ADMA) controller
10 The Tegra Audio DMA controller is used for transferring data
14 - Jon Hunter <jonathanh@nvidia.com>
17 - $ref: dma-controller.yaml#
22 - enum:
23 - nvidia,tegra210-adma
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Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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Dst_fdma.txt3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
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Drenesas,rcar-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car and RZ/G DMA Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: dma-controller.yaml#
18 - items:
19 - enum:
20 - renesas,dmac-r8a7742 # RZ/G1H
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/Documentation/driver-api/rapidio/
Dtsi721.rst2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
28 For mask definitions see 'drivers/rapidio/devices/tsi721.h'
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
34 descriptors allocated for each registered Tsi721 DMA channel.
37 - 'dma_txqueue_sz'
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/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-dma3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
17 GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.
21 DMA clients connected to the STM32 DMA3 controller must use the format
22 described in "#dma-cells" property description below, using a three-cell
23 specifier for each channel.
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
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Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
12 DMA clients connected to the STM32 MDMA controller must use the format
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
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Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
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/Documentation/devicetree/bindings/sound/
Dsnps,designware-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jose Abreu <joabreu@synopsys.com>
15 - items:
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
18 - enum:
19 - snps,designware-i2s
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/Documentation/crypto/
Dasync-tx-api.rst1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
43 xor-parity-calculations of the md-raid5 driver using the offload engines
53 2. cross channel dependency chains: the API allows a chain of dependent
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
56 to another implies a hardware channel switch.
64 -----------------------------
72 ------------------------
92 -------------------------
94 The return value is non-NULL and points to a 'descriptor' when the operation
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/Documentation/devicetree/bindings/crypto/
Dqcom-qce.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - const: qcom,crypto-v5.1
23 - const: qcom,crypto-v5.4
27 - items:
28 - enum:
29 - qcom,ipq4019-qce
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/Documentation/filesystems/spufs/
Dspu_run.rst1 .. SPDX-License-Identifier: GPL-2.0
10 spu_run - execute an spu context
25 Cell Broadband Engine Architecture in order to access Synergistic Pro-
26 cessor Units (SPUs). It uses the fd that was returned from spu_cre-
27 ate(2) to address a specific SPU context. When the context gets sched-
32 not return while the SPU is still running. If there is a need to exe-
42 gets filled when spu_run returns. It can be one of the following con-
46 A DMA alignment error
49 A DMA segmentation error
52 A DMA storage error
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Dspufs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
81 The first SPU to CPU communication mailbox. This file is read-only and
82 can be read in units of 32 bits. The file can only be used in non-
87 If a count smaller than four is requested, read returns -1 and
89 box, the return value is set to -1 and errno becomes EAGAIN.
101 If a count smaller than four is requested, read returns -1 and
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/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
7 Packet DMA.
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
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/Documentation/driver-api/dmaengine/
Dprovider.rst8 Most of the Slave DMA controllers have the same general principles of
11 They have a given number of channels to use for the DMA transfers, and
20 DMA-eligible devices to the controller itself. Whenever the device
21 will want to start a transfer, it will assert a DMA request (DRQ) by
24 A very simple DMA controller would only take into account a single
35 is why most if not all of the DMA controllers can adjust this, using a
38 Moreover, some DMA controllers, whenever the RAM is used as a source
44 transfer into smaller sub-transfers.
46 Our theoretical DMA controller would then only be able to do transfers
49 non-contiguous buffers to a contiguous buffer, which is called
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/Documentation/admin-guide/blockdev/
Dfloppy.rst19 Example: If your kernel is called linux-2.6.9, type the following line
22 linux-2.6.9 floppy=thinkpad
25 of linux-2.6.9::
31 linux-2.6.9 floppy=daring floppy=two_fdc
62 Sets the bit mask to allow only units 0 and 1. (default)
91 Tells the floppy driver not to use Dma for data transfers.
93 DMA channel for the floppy driver. This option is also useful
94 if you frequently get "Unable to allocate DMA memory" messages.
95 Indeed, dma memory needs to be continuous in physical memory,
96 and is thus harder to find, whereas non-dma buffers may be
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/Documentation/userspace-api/media/v4l/
Ddev-overlay.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
11 Video overlay devices have the ability to genlock (TV-)video into the
12 (VGA-)video signal of a graphics card, or to store captured images
43 advantage of memory mapping and DMA.
62 :ref:`streaming parameter <streaming-par>` ioctls as needed. The
77 privileged because it allows to set up DMA into physical memory,
93 1. Chroma-keying displays the overlaid image only where pixels in the
105 4. The framebuffer has an alpha channel that can be used to clip or
162 ------------------
181 When chroma-keying has been negotiated with
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/Documentation/driver-api/
Dlibata.rst12 transports for ATA and ATAPI devices, and SCSI<->ATA translation for ATA
16 internals, and a couple sample ATA low-level drivers.
22 is defined for every low-level libata
23 hardware driver, and it controls how the low-level driver interfaces
26 FIS-based drivers will hook into the system with ``->qc_prep()`` and
27 ``->qc_issue()`` high-level hooks. Hardware which behaves in a manner
33 ----------------------------------------------------------
35 Post-IDENTIFY device configuration
44 Typically used to apply device-specific fixups prior to issue of SET
45 FEATURES - XFER MODE, and prior to operation.
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