Searched +full:dma +full:- +full:coherent (Results 1 – 25 of 125) sorted by relevance
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| /Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
6 Required properties for DMA interfaces:
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
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| D | marvell,xor-v2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
19 - const: marvell,xor-v2
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| D | nvidia,tegra186-gpc-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPC DMA Controller
10 The Tegra General Purpose Central (GPC) DMA controller is used for faster
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Rajesh Gumasta <rgumasta@nvidia.com>
19 - $ref: dma-controller.yaml#
24 - const: nvidia,tegra186-gpcdma
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| D | arm,pl330.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/arm,pl330.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PrimeCell PL330 DMA Controller
10 - Vinod Koul <vkoul@kernel.org>
13 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
23 - compatible
26 - $ref: dma-controller.yaml#
27 - $ref: /schemas/arm/primecell.yaml#
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xlnx,zynqmp-dma-1.0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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| /Documentation/driver-api/usb/ |
| D | dma.rst | 1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
13 Documentation/core-api/dma-api-howto.rst). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
21 - URBs have an additional "transfer_dma" field, as well as a transfer_flags
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| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
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| D | fsl,ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - description: SATA controller for ls1012a
17 - const: fsl,ls1012a-ahci
18 - const: fsl,ls1043a-ahci
19 - enum:
20 - fsl,ls1021a-ahci
21 - fsl,ls1028a-ahci
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| /Documentation/devicetree/bindings/crypto/ |
| D | amd-ccp.txt | 4 - compatible: Should be "amd,ccp-seattle-v1a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the CCP interrupt
9 - dma-coherent: Present if dma operations are coherent
13 compatible = "amd,ccp-seattle-v1a";
15 interrupt-parent = <&gic>;
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| D | hisilicon,hip07-sec.txt | 4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
19 - dma-coherent: The driver assumes coherent dma is possible.
22 - iommus: The SEC units are behind smmu-v3 iommus.
23 Refer to iommu/arm,smmu-v3.txt for more information.
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| D | nvidia,tegra234-se-aes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
12 AES-CMAC
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-aes
30 dma-coherent: true
33 - compatible
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| D | nvidia,tegra234-se-hash.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Tegra Security HASH Engine accelerates the following HASH functions -
11 SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
15 - Akhil R <akhilrajeev@nvidia.com>
19 const: nvidia,tegra234-se-hash
30 dma-coherent: true
33 - compatible
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| /Documentation/devicetree/bindings/xillybus/ |
| D | xillybus.txt | 4 - compatible: Should be "xillybus,xillybus-1.00.a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Contains one interrupt node, typically consisting of three cells.
9 - dma-coherent: Present if DMA operations are coherent
14 compatible = "xillybus,xillybus-1.00.a";
17 interrupt-parent = <&intc>;
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| /Documentation/devicetree/bindings/pci/ |
| D | xgene-pci.txt | 1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
15 - dma-ranges: ranges for the inbound memory regions.
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| D | ti,am65-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
26 - const: app
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| D | ti,am65-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
25 reg-names:
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| D | sifive,fu740-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
24 const: sifive,fu740-pcie
29 reg-names:
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| D | layerscape-pcie-gen4.txt | 4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
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| /Documentation/devicetree/bindings/display/hisilicon/ |
| D | hisi-ade.txt | 1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
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| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
35 --------------------
36 - dma-coherent: Present if DMA operations made by the FlexRM engine (such
37 as DMA descriptor access, access to buffers pointed by DMA
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| /Documentation/devicetree/bindings/net/ |
| D | amd-xgbe.txt | 1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
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| /Documentation/devicetree/bindings/infiniband/ |
| D | hisilicon-hns-roce.txt | 10 - compatible: Should contain "hisilicon,hns-roce-v1".
11 - reg: Physical base address of the RoCE driver and
13 - eth-handle: phandle, specifies a reference to a node
15 - dsaf-handle: phandle, specifies a reference to a node
17 - node_guid: a number that uniquely identifies a device or component
18 - #address-cells: must be 2
19 - #size-cells: must be 2
21 - dma-coherent: Present if DMA operations are coherent.
22 - interrupts: should contain 32 completion event irq,1 async event irq
24 - interrupt-names:should be one of 34 irqs for roce device
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| /Documentation/devicetree/bindings/gpu/host1x/ |
| D | nvidia,tegra234-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
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| /Documentation/PCI/ |
| D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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