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/Documentation/devicetree/bindings/crypto/
Domap-des.txt5 - compatible : Should contain "ti,omap4-des"
6 - ti,hwmods: Name of the hwmod associated with the DES module
7 - reg : Offset and length of the register set for the module
8 - interrupts : the interrupt-specifier for the DES module
9 - clocks : A phandle to the functional clock node of the DES module
10 corresponding to each entry in clock-names
11 - clock-names : Name of the functional clock, should be "fck"
14 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
15 Documentation/devicetree/bindings/dma/dma.txt
16 Each entry corresponds to an entry in dma-names
[all …]
Dimg-hash.txt8 - compatible : "img,hash-accelerator"
9 - reg : Offset and length of the register set for the module, and the DMA port
10 - interrupts : The designated IRQ line for the hashing module.
11 - dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
12 - dma-names : Should be "tx"
13 - clocks : Clock specifiers
14 - clock-names : "sys" Used to clock the hash block registers
20 compatible = "img,hash-accelerator";
23 dmas = <&dma 8 0xffffffff 0>;
24 dma-names = "tx";
[all …]
Dstarfive,jh7110-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia Jie Ho <jiajie.ho@starfivetech.com>
11 - William Qiu <william.qiu@starfivetech.com>
16 - starfive,jh7110-crypto
17 - starfive,jh8100-crypto
24 - description: Hardware reference clock
25 - description: AHB reference clock
[all …]
/Documentation/devicetree/bindings/sound/
Dadi,axi-spdif-tx.txt1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
5 - reg : Must contain SPDIF core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
11 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
12 the core. The core expects one dma channel for transmit.
13 - dma-names : Must be "tx"
15 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
17 * resource-names.txt
[all …]
Dadi,axi-i2s.txt1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
15 the core. The core expects two dma channels if both transmit and receive are
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
21 * resource-names.txt
[all …]
Dallwinner,sun4i-a10-spdif.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Liam Girdwood <lgirdwood@gmail.com>
12 - Mark Brown <broonie@kernel.org>
13 - Maxime Ripard <mripard@kernel.org>
16 "#sound-dai-cells":
21 - const: allwinner,sun4i-a10-spdif
[all …]
Dallwinner,sun4i-a10-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#sound-dai-cells":
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
[all …]
Dhisilicon,hi6210-i2s.txt5 - compatible: should be one of the following:
6 - "hisilicon,hi6210-i2s"
7 - reg: physical base address of the i2s controller unit and length of
9 - interrupts: should contain the i2s interrupt.
10 - clocks: a list of phandle + clock-specifier pairs, one for each entry
11 in clock-names.
12 - clock-names: should contain following:
13 - "dacodec"
14 - "i2s-base"
15 - dmas: DMA specifiers for tx dma. See the DMA client binding,
[all …]
/Documentation/devicetree/bindings/dma/
Drenesas,rz-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
[all …]
Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
[all …]
Dsprd,sc9860-dma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
16 - Orson Zhai <orsonzhai@gmail.com>
17 - Baolin Wang <baolin.wang7@gmail.com>
[all …]
Dfsl,imx-dma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,imx-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller for i.MX
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dma-controller.yaml#
18 - fsl,imx1-dma
19 - fsl,imx21-dma
20 - fsl,imx27-dma
[all …]
Dlpc1850-dmamux.txt1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
[all …]
Dst_fdma.txt3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
[all …]
Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
12 node which contains the DMA request to channel mapping registers.
[all …]
Dnvidia,tegra20-apbdma.txt1 * NVIDIA Tegra APB DMA controller
4 - compatible: Should be "nvidia,<chip>-apbdma"
5 - reg: Should contain DMA registers location and length. This should include
6 all of the per-channel registers.
7 - interrupts: Should contain all of the per-channel DMA interrupts.
8 - clocks: Must contain one entry, for the module clock.
9 See ../clocks/clock-bindings.txt for details.
10 - resets : Must contain an entry for each entry in reset-names.
12 - reset-names : Must include the following entries:
13 - dma
[all …]
/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-dma.txt1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
13 ------------------
15 ------------------
17 |-> DMA instance #0
19 |-> DMA instance #1
[all …]
/Documentation/devicetree/bindings/usb/
Dda8xx-usb.txt3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
[all …]
Dux500-usb.txt4 - compatible : Should be "stericsson,db8500-musb"
5 - reg : Offset and length of registers
6 - interrupts : Interrupt; mode, number and trigger
7 - dr_mode : Dual-role; either host mode "host", peripheral mode "peripheral"
11 - dmas : A list of dma channels;
12 dma-controller, event-line, fixed-channel, flags
13 - dma-names : An ordered list of channel names affiliated to the above
18 compatible = "stericsson,db8500-musb";
21 interrupt-names = "mc";
25 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
[all …]
/Documentation/devicetree/bindings/spi/
Dmicrochip,spi-pic32.txt4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
[all …]
Dspi-sprd.txt4 - compatible: Should be "sprd,sc9860-spi".
5 - reg: Offset and length of SPI controller register space.
6 - interrupts: Should contain SPI interrupt.
7 - clock-names: Should contain following entries:
11 - clocks: List of clock input name strings sorted in the same order
12 as the clock-names property.
13 - #address-cells: The number of cells required to define a chip select
15 - #size-cells: Should be set to 0.
18 dma-names: Should contain names of the SPI used DMA channel.
19 dmas: Should contain DMA channels and DMA slave ids which the SPI used
[all …]
/Documentation/devicetree/bindings/mmc/
Dingenic,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: mmc-controller.yaml#
18 - enum:
19 - ingenic,jz4740-mmc
20 - ingenic,jz4725b-mmc
21 - ingenic,jz4760-mmc
22 - ingenic,jz4775-mmc
[all …]
/Documentation/devicetree/bindings/misc/
Datmel-ssc.txt4 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
5 - atmel,at91rm9200-ssc: support pdc transfer
6 - atmel,at91sam9g45-ssc: support dma transfer
7 - reg: Should contain SSC registers location and length
8 - interrupts: Should contain SSC interrupt
9 - clock-names: tuple listing input clock names.
11 - clocks: phandles to input clocks.
14 Required properties for devices compatible with "atmel,at91sam9g45-ssc":
15 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
16 the memory interface and SSC DMA channel ID (for tx and rx).
[all …]
/Documentation/devicetree/bindings/net/
Dqcom,bam-dmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,bam-dmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
15 or MSM8974. It is built using a simple protocol layer on top of a DMA engine
16 (Qualcomm BAM DMA) and bidirectional interrupts to coordinate power control.
20 DMA engine). As such it is specific to a firmware version, not a particular
25 const: qcom,bam-dmux
32 - description: Power control
[all …]
/Documentation/devicetree/bindings/gpu/host1x/
Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
[all …]

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