Home
last modified time | relevance | path

Searched +full:dma +full:- +full:window (Results 1 – 25 of 38) sorted by relevance

12

/Documentation/devicetree/bindings/tpm/
Dibm,vtpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nayna Jain <nayna@linux.ibm.com>
23 - IBM,vtpm
24 - IBM,vtpm20
30 - IBM,vtpm
31 - IBM,vtpm20
36 ibm,#dma-address-cells:
39 dma-window properties
[all …]
/Documentation/devicetree/bindings/iommu/
Diommu.txt13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
18 * Provide system protection against "rogue" DMA by forcing all accesses to go
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
[all …]
Dnvidia,tegra30-smmu.txt4 - compatible : "nvidia,tegra30-smmu"
5 - reg : Should contain 3 register banks(address and length) for each
7 - interrupts : Should contain MC General interrupt.
8 - nvidia,#asids : # of ASIDs
9 - dma-window : IOVA start address and length.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
14 compatible = "nvidia,tegra30-smmu";
19 dma-window = <0 0x40000000>; /* IOVA start & length */
Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
32 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
33 for window 1, 2 and 3.
42 const: samsung,exynos-sysmmu
[all …]
/Documentation/driver-api/
Dvme.rst5 -------------------
24 .. code-block:: c
30 if (vdev->id.num >= USER_BUS_MAX)
41 dev->bridge->num.
49 -------------------
53 succeeds, a non-zero value should be returned. A zero return value indicates
61 and/or dma channels (:c:func:`vme_dma_request`). Rather than allowing the device
62 driver to request a specific window or DMA channel (which may be used by a
69 attributes can be requested for a single window, the core will assign a window
71 should be used to identify the allocated resource when it is used. For DMA
[all …]
Dntb.rst5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
9 scratchpad and message registers. Scratchpad registers are read-and-writable
36 ----------------------------------------
40 mainly used to perform the proper memory window initialization. Typically
41 there are two types of memory window interfaces supported by the NTB API:
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
53 |------------| |--------------| | |--------------|
55 So typical scenario of the first type memory window initialization looks:
[all …]
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
5 Many modern systems now provide DMA and interrupt remapping facilities
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
12 safe [2]_, non-privileged, userspace drivers.
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
36 ---------------------------
40 and DMA. Without going into the details of each of these, DMA is
42 as allowing a device read-write access to system memory imposes the
[all …]
/Documentation/arch/powerpc/
Dpci_iov_resource_on_powernv.rst24 partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
57 - For DMA we then provide an entire address space for each PE that can
59 Each window can be configured to be remapped via a "TCE table" (IOMMU
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
76 window and sixteen M64 windows. They have different characteristics.
[all …]
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
[all …]
/Documentation/driver-api/rapidio/
Dmport_cdev.rst17 for user-space applications. Most of RapidIO operations are supported through
24 Using available set of ioctl commands user-space applications can perform
27 - Reads and writes from/to configuration registers of mport devices
29 - Reads and writes from/to configuration registers of remote RapidIO devices.
32 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
33 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
34 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
35 - Query capabilities and RapidIO link configuration of mport devices
37 - Enable/Disable reporting of RapidIO doorbell events to user-space applications
39 - Enable/Disable reporting of RIO port-write events to user-space applications
[all …]
Dtsi721.rst2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
14 destination IDs without need for changes in outbound window translation.
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
34 descriptors allocated for each registered Tsi721 DMA channel.
37 - 'dma_txqueue_sz'
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dmsi-pic.txt4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
[all …]
/Documentation/userspace-api/media/v4l/
Ddev-overlay.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
11 Video overlay devices have the ability to genlock (TV-)video into the
12 (VGA-)video signal of a graphics card, or to store captured images
17 video into a window.
43 advantage of memory mapping and DMA.
62 :ref:`streaming parameter <streaming-par>` ioctls as needed. The
77 privileged because it allows to set up DMA into physical memory,
93 1. Chroma-keying displays the overlaid image only where pixels in the
119 Overlay Window
122 The overlaid image is determined by cropping and overlay window
[all …]
/Documentation/devicetree/bindings/pci/
Dv3-v360epc-pci.txt6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
[all …]
Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
[all …]
Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
[all …]
Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
[all …]
/Documentation/devicetree/bindings/mmc/
Darm,pl18x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
[all …]
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
/Documentation/PCI/endpoint/
Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
12 machine, expose memory ranges as BARs, and perform DMA. They also support
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
[all …]
/Documentation/devicetree/bindings/display/
Datmel,lcdc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
17 interface and a look-up table to allow palletized display configurations. The
19 resolutions, window sizes, image formats and pixel depths.
26 - required: [ 'atmel,dmacon' ]
27 - required: [ 'atmel,lcdcon2' ]
[all …]
/Documentation/driver-api/dmaengine/
Dprovider.rst8 Most of the Slave DMA controllers have the same general principles of
11 They have a given number of channels to use for the DMA transfers, and
20 DMA-eligible devices to the controller itself. Whenever the device
21 will want to start a transfer, it will assert a DMA request (DRQ) by
24 A very simple DMA controller would only take into account a single
35 is why most if not all of the DMA controllers can adjust this, using a
38 Moreover, some DMA controllers, whenever the RAM is used as a source
44 transfer into smaller sub-transfers.
46 Our theoretical DMA controller would then only be able to do transfers
49 non-contiguous buffers to a contiguous buffer, which is called
[all …]
/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
[all …]
/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
/Documentation/admin-guide/media/
Drkisp1.rst1 .. SPDX-License-Identifier: GPL-2.0
14 rkisp1 and uses the Media-Controller API.
27 - RKISP1_V10: used at least in rk3288 and rk3399
28 - RKISP1_V11: declared in the original vendor code, but not used
29 - RKISP1_V12: used at least in rk3326 and px30
30 - RKISP1_V13: used at least in rk1808
36 .. kernel-figure:: rkisp1.dot
43 - rkisp1_mainpath: capture device for retrieving images, usually in higher
45 - rkisp1_selfpath: capture device for retrieving images.
46 - rkisp1_stats: a metadata capture device that sends statistics.
[all …]

12