| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | qcom,gpi.yaml | 4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
23 - qcom,sdm845-gpi-dma
24 - qcom,sm6350-gpi-dma
27 - qcom,qcm2290-gpi-dma
28 - qcom,qdu1000-gpi-dma
29 - qcom,sc7280-gpi-dma
30 - qcom,sdx75-gpi-dma
[all …]
|
| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
[all …]
|
| D | sprd,sc9860-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
22 const: sprd,sc9860-dma
33 - description: DMA enable clock
34 - description: optional ashb_eb clock, only for the AGCP DMA controller
42 '#dma-cells':
45 dma-channels:
[all …]
|
| D | owl-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
18 - $ref: dma-controller.yaml#
23 - actions,s500-dma
24 - actions,s700-dma
25 - actions,s900-dma
33 DMA channels.
[all …]
|
| D | intel,ldma.yaml | 4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
7 title: Lightning Mountain centralized DMA controllers.
14 - $ref: dma-controller.yaml#
31 "#dma-cells":
34 The first cell is the peripheral's DMA request line.
38 dma-channels:
42 dma-channel-mask:
58 intel,dma-poll-cnt:
61 DMA descriptor polling counter is used to control the poling mechanism
64 intel,dma-byte-en:
[all …]
|
| D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
8 the dma/dma.txt file for a more detailed description of binding.
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
22 dma0: dma@14000 {
[all …]
|
| D | fsl,mxs-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28
13 - $ref: dma-controller.yaml#
18 const: fsl,imx8qxp-dma-apbh
31 - fsl,imx6q-dma-apbh
32 - fsl,imx6sx-dma-apbh
33 - fsl,imx7d-dma-apbh
34 - fsl,imx8qxp-dma-apbh
35 - const: fsl,imx28-dma-apbh
37 - fsl,imx23-dma-apbh
[all …]
|
| D | allwinner,sun50i-a64-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#
7 title: Allwinner A64 DMA Controller
14 - $ref: dma-controller.yaml#
17 "#dma-cells":
24 - allwinner,sun20i-d1-dma
25 - allwinner,sun50i-a64-dma
26 - allwinner,sun50i-a100-dma
27 - allwinner,sun50i-h6-dma
29 - const: allwinner,sun8i-r40-dma
30 - const: allwinner,sun50i-a64-dma
[all …]
|
| D | fsl,imx-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/fsl,imx-dma.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller for i.MX
13 - $ref: dma-controller.yaml#
18 - fsl,imx1-dma
19 - fsl,imx21-dma
20 - fsl,imx27-dma
27 - description: DMA complete interrupt
28 - description: DMA Error interrupt
39 "#dma-cells":
42 dma-channels:
[all …]
|
| D | ingenic,dma.yaml | 4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
7 title: Ingenic SoCs DMA Controller
13 - $ref: dma-controller.yaml#
19 - ingenic,jz4740-dma
20 - ingenic,jz4725b-dma
21 - ingenic,jz4755-dma
22 - ingenic,jz4760-dma
25 - ingenic,jz4760b-dma
28 - ingenic,jz4770-dma
29 - ingenic,jz4780-dma
[all …]
|
| D | lpc1850-dmamux.txt | 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
19 dmac: dma@40002000 {
26 #dma-cells = <2>;
27 dma-channels = <8>;
[all …]
|
| D | moxa,moxart-dma.txt | 1 MOXA ART DMA Controller
3 See dma.txt first
7 - compatible : Must be "moxa,moxart-dma"
11 - #dma-cells : Should be 1, a single cell holding a line request number
15 dma: dma@90500000 {
16 compatible = "moxa,moxart-dma";
19 #dma-cells = <1>;
25 DMA clients connected to the MOXA ART DMA controller must use the format
26 described in the dma.txt file, using a two-cell specifier for each channel:
30 1. A phandle pointing to the DMA controller.
[all …]
|
| D | dma-router.yaml | 4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
7 title: DMA Router Common Properties
13 - $ref: dma-common.yaml#
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
23 pattern: "^dma-router(@.*)?$"
25 dma-masters:
30 Array of phandles to the DMA controllers the router can direct
33 dma-requests:
[all …]
|
| D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
20 dma0: dma@fcd02000 {
21 compatible = "hisilicon,k3-dma-1.0";
[all …]
|
| D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
52 dma-channels = <8>;
53 dma-requests = <8>;
56 * DMA client
60 dmas and dma-names are required, as described in dma.txt.
[all …]
|
| D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
6 Required properties for DMA interfaces:
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
11 1st - DMA control and status register address space.
15 - interrupts: DMA has 5 interrupts sources. 1st interrupt is
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
17 are completion interrupts for each DMA channels.
21 - dma-coherent : Present if dma operations are coherent
[all …]
|
| D | allwinner,sun6i-a31-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/allwinner,sun6i-a31-dma.yaml#
7 title: Allwinner A31 DMA Controller
14 - $ref: dma-controller.yaml#
17 "#dma-cells":
23 - allwinner,sun6i-a31-dma
24 - allwinner,sun8i-a23-dma
25 - allwinner,sun8i-a83t-dma
26 - allwinner,sun8i-h3-dma
27 - allwinner,sun8i-v3s-dma
42 - "#dma-cells"
[all …]
|
| D | dma-common.yaml | 4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
7 title: DMA Engine Common Properties
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
25 Used to provide DMA controller specific information.
27 dma-channel-mask:
29 Bitmask of available DMA channels in ascending order that are
40 dma-channels:
[all …]
|
| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
[all …]
|
| /Documentation/driver-api/ |
| D | dma-buf.rst | 1 Buffer Sharing and Synchronization (dma-buf)
4 The dma-buf subsystem provides the framework for sharing buffers for
5 hardware (DMA) access across multiple device drivers and subsystems, and
14 interact with the three main primitives offered by dma-buf:
16 - dma-buf, representing a sg_table and exposed to userspace as a file
19 - dma-fence, providing a mechanism to signal when an asynchronous
21 - dma-resv, which manages a set of dma-fences for a particular dma-buf
29 For more details on how to design your subsystem's API for dma-buf use, please
30 see Documentation/userspace-api/dma-buf-alloc-exchange.rst.
33 Shared DMA Buffers
[all …]
|
| /Documentation/devicetree/bindings/usb/ |
| D | ux500-usb.txt | 11 - dmas : A list of dma channels;
12 dma-controller, event-line, fixed-channel, flags
13 - dma-names : An ordered list of channel names affiliated to the above
25 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
26 <&dma 38 0 0x0>, /* Logical - MemToDev */
27 <&dma 37 0 0x2>, /* Logical - DevToMem */
28 <&dma 37 0 0x0>, /* Logical - MemToDev */
29 <&dma 36 0 0x2>, /* Logical - DevToMem */
30 <&dma 36 0 0x0>, /* Logical - MemToDev */
31 <&dma 19 0 0x2>, /* Logical - DevToMem */
[all …]
|
| /Documentation/core-api/ |
| D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
16 #include <linux/dma-mapping.h>
17 #include <asm/dma.h>
19 The first is the generic DMA API used to convert virtual addresses to
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
22 The second contains the routines specific to ISA DMA transfers. Since
30 The ISA DMA controller has some very strict requirements on which
[all …]
|
| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
17 3. A 32bit mask specifying the DMA channel configuration which are device
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
[all …]
|
| /Documentation/driver-api/usb/ |
| D | dma.rst | 1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
13 Documentation/core-api/dma-api-howto.rst). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
[all …]
|