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/Documentation/ABI/testing/
Dsysfs-bus-soundwire-slave67 What: /sys/bus/soundwire/devices/sdw:.../dp<N>_src/max_word
68 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/min_word
69 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/words
70 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/type
71 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/max_grouping
72 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/simple_ch_prep_sm
73 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/ch_prep_timeout
74 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/imp_def_interrupts
75 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/min_ch
76 /sys/bus/soundwire/devices/sdw:.../dp<N>_src/max_ch
[all …]
/Documentation/devicetree/bindings/display/
Ddp-aux-bus.yaml4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
19 To model this relationship, DP sinks should be placed as children
20 of the DP controller under the "aux-bus" node.
23 possible it will be extended in the future to handle the DP case.
24 For DP, presumably a connector would be listed under the DP AUX
/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
23 - qcom,sc8180x-dp
25 - qcom,sc8280xp-dp
27 - qcom,sdm845-dp
28 - qcom,sm8350-dp
29 - qcom,sm8650-dp
32 - qcom,sm6350-dp
33 - qcom,sm8150-dp
[all …]
/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-usb43dp-phy.yaml7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
23 - qcom,sdm845-qmp-usb3-dp-phy
24 - qcom,sm6350-qmp-usb3-dp-phy
25 - qcom,sm8150-qmp-usb3-dp-phy
26 - qcom,sm8250-qmp-usb3-dp-phy
27 - qcom,sm8350-qmp-usb3-dp-phy
28 - qcom,sm8450-qmp-usb3-dp-phy
[all …]
Dphy-rockchip-usbdp.yaml49 rockchip,dp-lane-mux:
57 determines the DisplayPort (DP) lane index, while the value of an entry
58 indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
59 e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
60 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
61 lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
62 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
63 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
64 DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
85 When select the DP lane mapping will request its phandle.
Dtransmit-amplitude.yaml78 - dp
79 - dp-rbr
80 - dp-hbr
81 - dp-hbr2
82 - dp-hbr3
83 - dp-uhbr-10
84 - dp-uhbr-13.5
85 - dp-uhbr-20
Dsamsung,dp-video-phy.yaml4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
38 compatible = "samsung,exynos5420-dp-video-phy";
Drockchip,rk3288-dp-phy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
14 const: rockchip,rk3288-dp-phy
37 compatible = "rockchip,rk3288-dp-phy";
Dphy-rockchip-typec.txt22 The sub-node name is used to identify dp or usb3 port,
24 * "dp-port" : the name of DP port.
53 tcphy0_dp: dp-port {
77 tcphy1_dp: dp-port {
/Documentation/devicetree/bindings/display/rockchip/
Drockchip,analogix-dp.yaml4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
16 - rockchip,rk3288-dp
26 - const: dp
37 const: dp
53 - $ref: /schemas/display/bridge/analogix,dp.yaml#
62 dp@ff970000 {
63 compatible = "rockchip,rk3288-dp";
67 clock-names = "dp", "pclk";
69 phy-names = "dp";
71 reset-names = "dp";
Dcdn-dp-rockchip.txt5 - compatible: must be "rockchip,rk3399-cdn-dp"
9 - clocks: from common clock binding: handle to dp clock.
20 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
37 cdn_dp: dp@fec00000 {
38 compatible = "rockchip,rk3399-cdn-dp";
/Documentation/devicetree/bindings/clock/
Dqcom,sm8450-dispcc.yaml34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
38 - description: Link clock from DP PHY2
39 - description: VCO DIV clock from DP PHY2
40 - description: Link clock from DP PHY3
41 - description: VCO DIV clock from DP PHY3
Dqcom,sm8550-dispcc.yaml39 - description: Link clock from DP PHY0
40 - description: VCO DIV clock from DP PHY0
41 - description: Link clock from DP PHY1
42 - description: VCO DIV clock from DP PHY1
43 - description: Link clock from DP PHY2
44 - description: VCO DIV clock from DP PHY2
45 - description: Link clock from DP PHY3
46 - description: VCO DIV clock from DP PHY3
/Documentation/netlink/specs/
Dovs_datapath.yaml17 name: dp-ifindex
22 name-prefix: ovs-dp-f-
39 enum-name: ovs-dp-stats
56 enum-name: ovs-dp-megaflow-stats
78 name-prefix: ovs-dp-attr-
117 name-prefix: ovs-dp-cmd-
124 do: &dp-get-op
137 dump: *dp-get-op
/Documentation/devicetree/bindings/display/connector/
Ddp-connector.yaml4 $id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
14 const: dp-connector
27 dp-pwr-supply:
32 description: Connection to controller providing DP signals
44 compatible = "dp-connector";
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra124-sor.yaml15 and DP outputs.
60 avdd-io-hdmi-dp-supply:
61 description: I/O supply for HDMI/DP
63 vdd-hdmi-dp-pll-supply:
64 description: PLL supply for HDMI/DP
130 - const: dp
151 - const: dp
164 - avdd-io-hdmi-dp-supply
165 - vdd-hdmi-dp-pll-supply
182 clock-names = "sor", "out", "parent", "dp", "safe";
[all …]
/Documentation/sound/hd-audio/
Ddp-mst.rst2 HD-Audio DP-MST Support
5 To support DP MST audio, HD Audio hdmi codec driver introduces virtual pin
8 Virtual pin is an extension of per_pin. The most difference of DP MST
9 from legacy is that DP MST introduces device entry. Each pin can contain
25 the device entries number is dynamically changed. If DP MST hub is connected,
26 it is in DP MST mode, and the device entries number is 3. Otherwise, the
30 when bootup no matter whether it is in DP MST mode or not.
34 DP MST reuses connection list code. The code can be reused because
37 This means DP MST gets the device entry connection list without the
/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml41 DP bridge clock, used by the IP to know how to translate a number of
42 clock cycles into a time (which is used to comply with DP standard timings
67 First input port representing the DP bridge input.
72 Second input port representing the DP bridge input.
77 Third input port representing the DP bridge input.
82 Fourth input port representing the DP bridge input.
87 Output port representing the DP bridge output.
135 mhdp: dp-bridge@f0fb000000 {
Dmegachips-stdpxxxx-ge-b850v3-fw.txt2 STDP4028-ge-b850v3-fw bridges (LVDS-DP)
3 STDP2690-ge-b850v3-fw bridges (DP-DP++)
7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
Danalogix,dp.yaml4 $id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
26 const: dp
51 Port node with one endpoint connected to a dp-connector node.
Dtoshiba,tc358767.yaml14 converts DSI/DPI to eDP/DP .
98 eDP/DP output port. The remote endpoint phandle should be a
100 optional, treated as DP panel if not defined
110 Display port output Pre-Emphasis settings for both DP lanes.
177 /* DPI input and DP output */
/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos5-dp.yaml4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
17 const: samsung,exynos5-dp
27 - const: dp
45 - const: dp
75 Port node with one endpoint connected to a dp-connector node.
137 dp-controller@145b0000 {
138 compatible = "samsung,exynos5-dp";
141 clock-names = "dp";
145 phy-names = "dp";
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dp.yaml4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
14 MediaTek DP and eDP are different hardwares and there are some features
17 In addition, We just need to enable the power domain of DP, so the clock
18 of DP is generated by itself and we are not using other PLL to generate
24 - mediatek,mt8188-dp-tx
26 - mediatek,mt8195-dp-tx
95 compatible = "mediatek,mt8195-dp-tx";
/Documentation/devicetree/bindings/soc/samsung/
Dexynos-pmu.yaml91 dp-phy:
92 $ref: /schemas/phy/samsung,dp-video-phy.yaml
182 dp-phy: true
185 dp-phy: false
201 dp-phy {
202 compatible = "samsung,exynos5250-dp-video-phy";
/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml55 - const: dp
111 description: PHYs for the DP data lanes
117 - const: dp-phy0
118 - const: dp-phy1
187 reg-names = "dp", "blend", "av_buf", "aud";
206 phy-names = "dp-phy0", "dp-phy1";

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