Searched full:dpll (Results 1 – 12 of 12) sorted by relevance
| /Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
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| D | apll.txt | 9 a subtype of a DPLL [2], although a simplified one at that.
12 [2] Documentation/devicetree/bindings/clock/ti/dpll.txt
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| /Documentation/netlink/specs/ |
| D | dpll.yaml | 3 name: dpll
5 doc: DPLL subsystem.
12 working modes a dpll can support, differentiates if and how dpll selects
18 doc: input can be only selected by sending a request to dpll
22 doc: highest prio input pin auto selected by dpll
28 provides information of dpll device lock status, valid values for
34 dpll was not yet locked to any valid input (or forced by setting
40 dpll is locked to a valid signal, but no holdover available
44 dpll is locked and holdover acquired
48 dpll is in holdover state - lost a valid lock or was forced
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| D | rt_link.yaml | 1136 name: dpll-pin
1138 nested-attributes: link-dpll-pin-attrs
2130 name: link-dpll-pin-attrs
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| /Documentation/driver-api/ |
| D | dpll.rst | 4 The Linux kernel dpll subsystem
7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
22 The main purpose of dpll subsystem is to provide general interface
32 Single dpll device object means single Digital PLL circuit and bunch of
38 Changing the configuration of dpll device is done with `do` request of
52 The number of pins per dpll vary, but usually multiple pins shall be
53 provided for a single dpll device.
68 In general, selected pin (the one which signal is driving the dpll
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| D | index.rst | 87 dpll
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| /Documentation/devicetree/bindings/clock/ |
| D | microchip,sparx5-dpll.yaml | 4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
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| D | sprd,sc9863a-clk.yaml | 29 - sprd,sc9863a-dpll
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | adv748x.yaml | 38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
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| /Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
46 * "dpll_ref" - external dpll ref clk
47 * "dpll_ref_m2" - external dpll ref clk
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| /Documentation/networking/device_drivers/hamradio/ |
| D | z8530drv.rst | 227 cards. Use "mode dpll" for clock source (see below).
268 clock dpll # clock source:
269 # dpll = normal half duplex operation
308 present at all (BayCom). It feeds back the output of the DPLL
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| /Documentation/arch/arm/omap/ |
| D | dss.rst | 32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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