Home
last modified time | relevance | path

Searched +full:drive +full:- +full:strength (Results 1 – 25 of 116) sorted by relevance

12345

/Documentation/devicetree/bindings/pinctrl/
Drealtek,rtd1315e-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1315E is a high-definition media processor SoC. The
16 resistor, drive strength, schmitt trigger and power source.
20 const: realtek,rtd1315e-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
[all …]
Drealtek,rtd1619b-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1619b-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1619B is a high-definition media processor SoC. The
16 resistor, drive strength, schmitt trigger and power source.
20 const: realtek,rtd1619b-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
[all …]
Drealtek,rtd1319d-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1319D is a high-definition media processor SoC. The
16 resistor, drive strength, schmitt trigger and power source.
20 const: realtek,rtd1319d-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
[all …]
Dpincfg-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
[all …]
Dstarfive,jh7110-sys-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
13 can be multiplexed and have configurable bias, drive strength,
21 - Jianlong Huang <jianlong.huang@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
41 '#interrupt-cells':
[all …]
Dstarfive,jh7110-aon-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
13 can be multiplexed and have configurable bias, drive strength,
18 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
[all …]
Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
14 configurable bias, drive strength, schmitt trigger etc. The SoC has an
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
[all …]
Dqcom,msm8974-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8974-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
Dsocionext,uniphier-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Masahiro Yamada <yamada.masahiro@socionext.com>
16 - socionext,uniphier-ld4-pinctrl
17 - socionext,uniphier-pro4-pinctrl
18 - socionext,uniphier-sld8-pinctrl
19 - socionext,uniphier-pro5-pinctrl
20 - socionext,uniphier-pxs2-pinctrl
[all …]
Dmediatek,mt8183-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
17 const: mediatek,mt8183-pinctrl
23 reg-names:
25 - const: iocfg0
26 - const: iocfg1
27 - const: iocfg2
[all …]
Dbrcm,iproc-gpio.txt5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
[all …]
Dfsl,mxs-pinctrl.txt5 function is GPIO. The configuration on the pins includes drive strength,
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
19 In other words, a subnode that describes a drive strength parameter implies no
20 information about pull-up. For this reason, even seemingly boolean values are
34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
37 "pinctrl-*" phandle in client device node should only have one group node
41 Required subnode-properties:
[all …]
Dqcom,sm6115-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Iskren Chernev <iskren.chernev@gmail.com>
18 const: qcom,sm6115-tlmm
23 reg-names:
25 - const: west
26 - const: south
27 - const: east
[all …]
Datmel,at91-pio4-pinctrl.txt7 - compatible:
8 "atmel,sama5d2-pinctrl"
9 "microchip,sama7g5-pinctrl"
10 - reg: base address and length of the PIO controller.
11 - interrupts: interrupt outputs from the controller, one for each bank.
12 - interrupt-controller: mark the device node as an interrupt controller.
13 - #interrupt-cells: should be two.
14 - gpio-controller: mark the device node as a gpio controller.
15 - #gpio-cells: should be two.
17 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
[all …]
Dsprd,sc9860-pinctrl.txt7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
[all …]
Dtoshiba,visconti-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
18 - toshiba,tmpv7708-pinctrl
24 - $ref: pinctrl.yaml#
27 - compatible
28 - reg
31 '-pins$':
[all …]
Daxis,artpec6-pinctrl.txt1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
11 drive strength and bias pullup of the pin group. If either of these options is
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
[all …]
Dbrcm,ns2-pinmux.txt8 - compatible:
9 Must be "brcm,ns2-pinmux"
11 - reg:
17 - function:
20 - groups:
23 - pins:
26 The generic properties bias-disable, bias-pull-down, bias-pull-up,
27 drive-strength, slew-rate, input-enable, input-disable are supported
31 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
36 compatible = "brcm,ns2-pinmux";
[all …]
Dqcom,msm8960-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8960-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
[all …]
Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
[all …]
Dsophgo,cv1800-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@outlook.com>
15 - sophgo,cv1800b-pinctrl
16 - sophgo,cv1812h-pinctrl
17 - sophgo,sg2000-pinctrl
18 - sophgo,sg2002-pinctrl
22 - description: pinctrl for system domain
[all …]
/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
[all …]
/Documentation/devicetree/bindings/net/dsa/
Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
[all …]

12345