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/Documentation/devicetree/bindings/display/msm/
Ddsi-controller-main.yaml4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
7 title: Qualcomm Display DSI controller
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8976-dsi-ctrl
23 - qcom,msm8996-dsi-ctrl
24 - qcom,msm8998-dsi-ctrl
[all …]
Ddsi-phy-7nm.yaml4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
7 title: Qualcomm Display DSI 7nm PHY
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-7nm
19 - qcom,dsi-phy-7nm-8150
20 - qcom,sc7280-dsi-phy-7nm
21 - qcom,sm6375-dsi-phy-7nm
22 - qcom,sm8350-dsi-phy-5nm
23 - qcom,sm8450-dsi-phy-5nm
24 - qcom,sm8550-dsi-phy-4nm
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Ddsi-phy-28nm.yaml4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
7 title: Qualcomm Display DSI 28nm PHY
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-28nm-8226
19 - qcom,dsi-phy-28nm-8937
20 - qcom,dsi-phy-28nm-8960
21 - qcom,dsi-phy-28nm-hpm
22 - qcom,dsi-phy-28nm-hpm-fam-b
23 - qcom,dsi-phy-28nm-lp
27 - description: dsi pll register set
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Ddsi-phy-14nm.yaml4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
7 title: Qualcomm Display DSI 14nm PHY
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-2290
20 - qcom,dsi-phy-14nm-660
21 - qcom,dsi-phy-14nm-8953
22 - qcom,sm6125-dsi-phy-14nm
26 - description: dsi phy register set
27 - description: dsi phy lane register set
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Ddsi-phy-20nm.yaml4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
7 title: Qualcomm Display DSI 20nm PHY
13 - $ref: dsi-phy-common.yaml#
17 const: qcom,dsi-phy-20nm
21 - description: dsi pll register set
22 - description: dsi phy register set
23 - description: dsi phy regulator register set
51 dsi-phy@fd922a00 {
52 compatible = "qcom,dsi-phy-20nm";
/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml85 - description: DSI phy instance 1 dsi clock
86 - description: DSI phy instance 1 byte clock
87 - description: DSI phy instance 2 dsi clock
88 - description: DSI phy instance 2 byte clock
117 - description: DSI phy instance 0 dsi clock
118 - description: DSI phy instance 0 byte clock
145 - description: DSI phy instance 0 dsi clock
146 - description: DSI phy instance 0 byte clock
147 - description: DSI phy instance 1 dsi clock
148 - description: DSI phy instance 1 byte clock
[all …]
/Documentation/devicetree/bindings/display/
Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
34 conjunction with another DSI host to drive the same peripheral. Hardware
[all …]
Dallwinner,sun6i-a31-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
19 - allwinner,sun50i-a100-mipi-dsi
21 - const: allwinner,sun20i-d1-mipi-dsi
22 - const: allwinner,sun50i-a100-mipi-dsi
44 vcc-dsi-supply:
45 description: VCC-DSI power supply of the DSI encoder
70 - $ref: dsi-controller.yaml#
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Ddsi-controller.yaml4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
7 title: Common Properties for DSI Display Panels
13 This document defines device tree properties common to DSI, Display
22 Notice: this binding concerns DSI panels connected directly to a master
23 without any intermediate port graph to the panel. Each DSI master
31 pattern: "^dsi(@.*)?$"
37 another DSI host to drive the same peripheral. Hardware supporting
39 to be driven by the same clock. Only the DSI host instance
50 description: Panels connected to the DSI link
58 The virtual channel number of a DSI peripheral. Must be in the range
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Dst,stm32-dsi.yaml4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
7 title: STMicroelectronics STM32 DSI host controller
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
29 - description: DSI bus clock
47 phy-dsi-supply:
58 DSI input port node, connected to the ltdc rgb output port.
64 DSI output port node, connected to a panel or a bridge input port.
91 dsi: dsi@5a000000 {
[all …]
Dbrcm,bcm2835-dsi0.yaml7 title: Broadcom VC4 (VideoCore4) DSI Controller
13 - $ref: dsi-controller.yaml#
30 - description: The DSI PLL clock feeding the DSI analog PHY
31 - description: The DSI ESC clock
32 - description: The DSI pixel clock
43 # - description: The DSI byte clock for the PHY
44 # - description: The DSI DDR2 clock
45 # - description: The DSI DDR clock
68 dsi1: dsi@7e700000 {
Dtruly,nt35597.txt1 Truly model NT35597 DSI display driver
18 for single DSI or Dual DSI
19 This should be low for dual DSI and high for single DSI mode
23 - port@0: DSI input port driven by master DSI
24 - port@1: DSI input port driven by secondary DSI
28 dsi@ae94000 {
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-dsi.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
20 - nvidia,tegra124-dsi
21 - nvidia,tegra210-dsi
22 - nvidia,tegra186-dsi
25 - const: nvidia,tegra132-dsi
26 - const: nvidia,tegra124-dsi
48 - const: dsi
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/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
7 title: MediaTek DSI Controller
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 - $ref: /schemas/display/dsi-controller.yaml#
26 - mediatek,mt2701-dsi
27 - mediatek,mt7623-dsi
28 - mediatek,mt8167-dsi
29 - mediatek,mt8173-dsi
30 - mediatek,mt8183-dsi
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/Documentation/devicetree/bindings/display/bridge/
Drenesas,dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
36 - description: DSI Packet Receive interrupt
37 - description: DSI Fatal Error interrupt
[all …]
Drenesas,dsi-csi2-tx.yaml4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
21 - renesas,r8a779g0-dsi-csi2-tx # for V4H
29 - description: DSI (and CSI-2) functional clock
35 - const: dsi
55 description: DSI/CSI-2 output port
89 dsi0: dsi-encoder@fed80000 {
[all …]
Dintel,keembay-dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml#
7 title: Intel Keem Bay mipi dsi controller
15 const: intel,keembay-dsi
27 - description: MIPI DSI clock
28 - description: MIPI DSI econfig clock
29 - description: MIPI DSI config clock
43 description: MIPI DSI input port.
47 description: DSI output port.
65 mipi-dsi@20900000 {
66 compatible = "intel,keembay-dsi";
Dcdns,dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
7 title: Cadence DSI bridge
13 CDNS DSI is a bridge device which converts DPI to DSI
18 - cdns,dsi
19 - ti,j721e-dsi
61 Output port representing the DSI output. It can have
63 the DSI virtual channel used by this device.
74 - $ref: ../dsi-controller.yaml#
80 const: ti,j721e-dsi
111 dsi@fd0c0000 {
[all …]
Dnwl-dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
22 const: fsl,imx8mq-nwl-dsi
42 - description: DSI core clock
74 - description: dsi byte reset line
75 - description: dsi dpi reset line
76 - description: dsi esc reset line
[all …]
/Documentation/devicetree/bindings/display/rockchip/
Drockchip,dw-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
19 - rockchip,rk3288-mipi-dsi
20 - rockchip,rk3399-mipi-dsi
21 - rockchip,rk3568-mipi-dsi
22 - rockchip,rv1126-mipi-dsi
23 - const: snps,dw-mipi-dsi
74 - $ref: /schemas/display/bridge/snps,dw-mipi-dsi.yaml#
[all …]
/Documentation/devicetree/bindings/display/hisilicon/
Ddw-dsi.txt1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
11 - ports: contains DSI controller input and output sub port.
21 dsi: dsi@f4107800 {
22 compatible = "hisilicon,hi6220-dsi";
44 &dsi {
/Documentation/devicetree/bindings/display/panel/
Dsharp,lq101r1sx01.yaml13 This panel requires a dual-channel DSI host to operate. It supports two modes:
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
22 Note that in video mode the DSI-LINK1 interface always provides the left/even
23 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
49 phandle to the DSI peripheral on the secondary link. Note that the
50 presence of this property marks the containing node as DSI-LINK1
67 dsi0: dsi@fd922800 {
83 dsi1: dsi@fd922a00 {
Djdi,lpm102a188a.yaml7 title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1) is considered the primary peripheral
20 peripheral driven by the second link (DSI-LINK2).
43 phandle to the DSI peripheral on the secondary link. Note that the
44 presence of this property marks the containing node as DSI-LINK1.
67 dsia: dsi@54300000 {
78 dsib: dsi@54400000{
Dpanel-dsi-cm.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-dsi-cm.yaml#
7 title: DSI command mode panels
14 This binding file is a collection of the DSI panels that
16 referenced via the optional backlight property, the DSI
33 - const: panel-dsi-cm # Generic DSI command mode panel compatible fallback
37 description: DSI virtual channel
75 dsi-controller {
80 compatible = "tpo,taal", "panel-dsi-cm";
/Documentation/devicetree/bindings/phy/
Drockchip,px30-dsi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
22 - rockchip,rv1126-dsi-dphy
63 compatible = "rockchip,px30-dsi-dphy";

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